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AR# 30631

LogiCORE IP 3GPP LTE Turbo Encoder - Release Notes and Known Issues

Description

This Answer Record contains the Release Notes and Known Issues list for the CORE Generator software and LogiCORE IP 3GPP LTE Turbo Encoder Core.The following information is listed for each version of the core:

  • New Features
  • Resolved Issues
  • Known Issues

Solution

General LogiCORE IP 3GPP LTE Turbo Encoder Issues

LogiCORE IP 3GPP LTE Turbo Encoder v3.1

Initial Release in ISE Design Suite 12.1

New Features

  • ISE 12.1 software support

Resolved Issues

Known Issues (ISE)

  • N/A

Known Issues (Vivado)

  • (Xilinx Answer 53465) 2012.4 Vivado Simulator - Why does my DSP Digital Communications core fail to simulate with error Error: Failed to find design work <Core name>?

LogiCORE IP 3GPP LTE Turbo Encoder v3.0

Initial Release in ISE Design Suite 11.1

New Features

  • ISE 11.1 software support

Resolved Issues

  • N/A

Known Issues

  • Release Notes/README for 3GPP LTE Turbo Encoder v3.0 rev 1 Patch, see (Xilinx Answer 33617).
  • Why do I receive the following error message "ERROR:coreutil - XST has returned an error: ERROR:HDLCompiler:432"? See (Xilinx Answer 33618).

LogiCORE IP 3GPP LTE Turbo Encoder v2.0

Initial Release in ISE Design Suite 10.1 IP Update 3

New Features

  • ISE 10.1 software support
  • New FIFO-based memory architecture to optimize throughput for varying block sizes

Resolved Issues

  • N/A

Known Issues

  • N/A

LogiCORE IP 3GPP LTE Turbo Encoder v1.0

Initial Release in ISE Design Suite 10.1 IP Update 1

New Features

  • Drop-in module for Virtex-4, Virtex-5, and Spartan-3 FPGAs
  • Implements the 3GPP LTE specification
  • Core contains the full 3GPP LTE interleaver
  • All 188 3GPP LTE block sizes (40 - 6144) supported
  • Double-buffered symbol memory for maximum throughput

Resolved Issues

  • N/A

Known Issues

  • N/A
AR# 30631
Date Created 04/15/2008
Last Updated 01/02/2013
Status Active
Type Release Notes
IP
  • 3GPP LTE Turbo Encoder