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AR# 30634

LogiCORE Initiator/Target for PCI-X v6.7 - Release Notes and Known Issues for ISE 10.1 IP Update 1 (IP_10.1.1)

Description

This Release Note and Known Issues Answer Record is for the LogiCORE Initiator/Target for PCI-X v6.7 released in ISE 10.1 IP Update 1 and contains the following information:

- General Information

- New Features

- Bug Fixes

- Known Issues

For installation instructions, general CORE Generator known issues, and design tools requirements, see the IP Release Notes Guide at: http://www.xilinx.com/support/documentation/user_guides/xtp025.pdf

Solution

General Information

The LogiCORE PCI v6.7 supports Virtex-5 and newer architectures only. For all other devices, use the v5.165 PCI-X Core. For more information on this core, refer to (Xilinx Answer 30118).

New Features

- Added support for 10.1 SP1

Resolved Issues

CR 455162 - PCI-X Core no longer meets timing in ISE 10.1

ISE 10.1 reports timing failure on a design that ISE 9.2i and earlier reported as meeting timing. ISE 10.1 is correct; previous versions erroneously reported timing success resulting from a faulty PLL timing model. This required a change to the internal clocking structure. A DCM is now used to generate the global clock.

CR 447306 - Unusually low Latency Timer setting can cause faulty IRDY# disconnect sequence in PCI-X mode

When initiating a transaction, the Initiator/Target for PCI-X incorrectly deasserts IRDY# after the first ADB (but leaves FRAME# asserted) if ALL the following conditions are met:

- The transaction starts three or fewer data phases before the next ADB

- GNT# is deasserted between the first assertion of FRAME# and the first assertion of TRDY#

- The latency count expires before the first assertion of TRDY#

Known Issues

- See (Xilinx Answer 30518) regarding use of RCLK in embedded designs for PCI-X 133 MHz.

- CR472742: Timing issues might occur with certain devices for PCI-X 133 or 66 MHz designs. To fix this issue, open the UCF and locate the DESKEW_ADJUST parameter applied to the DCM. The correct setting for this parameter is as follows:

PCI-X 133 MHz:

XC5VLX110T: 7

All other devices: 8

PCI-X 66 MHz

XC5VLX110, LX110T, FX70T and FX100T: 7

All other devices: 8

- Refer to the release notes text file,"pcix_release_notes.txt," delivered with the core for known issues at the time of the release.

Revision History

05/07/2008 - Added CR472742; changed reference to AR30518.

04/18/2008 - Initial release

AR# 30634
Date Created 04/18/2008
Last Updated 12/15/2012
Status Active
Type General Article