AR #30638 - 11.1 ISE - Adding HDL source to project incorrectly marks process status as out-of-date
11.1 ISE - Adding HDL source to project incorrectly marks process status as out-of-date
| AR# | 30638 |
| Part | SW-Project Navigator |
| Last Modified | 2009-04-25 00:00:00.0 |
| Status | Active |
| Keywords | Verilog, VHDL, cancel, hierarchy, question mark, implement, synthesize, translate, MAP, PAR, copy, source, new |
Description
Keywords: Verilog, VHDL, cancel, hierarchy, question mark, implement, synthesize, translate, MAP, PAR, copy, source, new
After running any of the synthesis or implementation processes, I add a new Verilog or VHDL source to the project using one of the following methods:
- Project -> Add Source...
- Project -> Add Copy of Source ...
- Project -> New Source ...
Even though the added HDL source is not part of the hierarchy of the implemented top-level design, the completed processes are marked out-of-date.
Additionally, with the Add Source and Add Copy of Source processes, even if I select the Cancel option in the Adding Source Files ... window, the processes are still out of date.
Adding schematic, IP core, and HDL testbench sources does not set the status of processes out-of-date.
Solution
The operation to check the HDL source files does not check based on the hierarchy of the design, and, consequently, sets the status as out-of-date (incorrectly in many cases) any time an HDL file is added (or parsed for adding) to a project.In ISE 10.1 and later, if the added file does not affect the top-level design and the design has not otherwise changed, you can safely force the status of a process and continue implementation from the subsequent process. To do this, select the process to force and select Process -> Force Process Up-to-Date.