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10.1 SimPrims - Output of X_IDELAY is 'X' in VCS Verilog Simulation

AR# 30646

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Topic SW-Sim Libraries
Last Updated 04/01/2008
Status Active
Description

Keywords: x, unknown, idelay, timing, SimPrim

In 10.1 VCS Verilog simulation, the output of the X_IDELAY component in the simprims library is 'X'.

Solution

This issue will be fixed in 10.1 sp2.
 
 
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