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AR# 30646

10.1 SimPrims - Output of X_IDELAY is 'X' in VCS Verilog Simulation

Description

In 10.1 VCS Verilog simulation, the output of the X_IDELAY component in the simprims library is 'X'.

Solution

This issue will be fixed in 10.1 sp2.

AR# 30646
Date Created 04/01/2008
Last Updated 05/22/2014
Status Archive
Type General Article