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AR# 30647

LogiCORE Ethernet 1000BASE-X PCS/PMA or SGMII v9.1 - Virtex-5 GTX VCS Verilog functional and timing simulation errors out and does not complete

Description

Virtex-5 GTX VCS verilog functional and timing simulation error out and do not complete. This affects only simulations using GTX. It does not affect simulations using Virtex-5 GTP or Virtex-4 GT11 simulations.

Solution

To fix this issue for functional simulation in the simulation/functional/simulate_vcs.sh, change the line: 

 

$Xilinx/virtex5/smartmodel/lin/wrappers/vcsmxverilog/GTX_DUAL_SWIFT.v \ 

to: 

$Xilinx/smartmodel/lin/wrappers/vcsmxverilog/GTX_DUAL_SWIFT.v \ 

 

To fix this issue for timing simulation in the simulation/timing/simulate_vcs.sh, change the line: 

 

$Xilinx/smartmodel/lin/wrappers/vcsmxverilog/GTP_DUAL_SWIFT.v 

to: 

$Xilinx/smartmodel/lin/wrappers/vcsmxverilog/GTX_DUAL_SWIFT.v

AR# 30647
Date Created 04/01/2008
Last Updated 05/22/2014
Status Archive
Type General Article