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AR# 30668

LogiCORE Endpoint Block Plus for PCI Express v1.6.1 - Hold violations are reported for x4 and x1 designs using 10.1

Description

When implementing x4 and x1 Block Plus Core designs in 10.1, the Timing Analyzer reports the following failure:

"Hold Violations: PERIOD analysis for net "ep/BU2/U0/pcie_ep0/pcie_blk/clocking_i/clkout0" derived from NET "sys_clk_c" PERIOD = 10 ns HIGH 50%; divided by 2.50 to 4 nS

--------------------------------------------------------------------------------

Hold Violation: -0.316ns (requirement - (clock path skew + uncertainty - data path))

Source: ep/BU2/U0/pcie_ep0/pcie_blk/pcie_ep (CPU)

Destination: ep/BU2/U0/pcie_ep0/pcie_blk/prod_mim_fixes_I/sync_fifo_mim_I/full (FF)

Requirement: 0.000ns

Data Path Delay: 0.131ns (Levels of Logic = 1)

Positive Clock Path Skew: 0.234ns

Source Clock: trn_clk_c rising at 0.000ns

Destination Clock: ep/BU2/U0/pcie_ep0/core_clk rising at 4.000ns

Clock Uncertainty: 0.213ns

Timing Improvement Wizard

Data Path: ep/BU2/U0/pcie_ep0/pcie_blk/pcie_ep to ep/BU2/U0/pcie_ep0/pcie_blk/prod_mim_fixes_I/sync_fifo_mim_I/full

Delay type Delay(ns) Logical Resource(s)

---------------------------- -------------------

Tpcicko_RXRAM -0.213 ep/BU2/U0/pcie_ep0/pcie_blk/pcie_ep

net (fanout=12) 0.541 ep/BU2/U0/pcie_ep0/pcie_blk/mim_rx_bren

Tah (-Th) 0.197 ep/BU2/U0/pcie_ep0/pcie_blk/prod_mim_fixes_I/sync_fifo_mim_I/data_count_int_not00031

ep/BU2/U0/pcie_ep0/pcie_blk/prod_mim_fixes_I/sync_fifo_mim_I/full

---------------------------- ---------------------------

Total 0.131ns (-0.410ns logic, 0.541ns route)"

Solution

This is a known issue and is scheduled to be fixed in 10.1 SP3.

Revision History

04/03/2008 - Initial release

AR# 30668
Date Created 04/03/2008
Last Updated 12/15/2012
Status Active
Type General Article