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AR# 30702

MIG v2.1 - Virtex-5 DDR2 SDRAM 144-bit ECC design fails during synthesis

Description

The MIG v2.1 DDR2 SDRAM design for Virtex-5 FPGAhas an error in the usr_rd.v/.vhd file for a 144-bit ECC design. This error causes multi-source errors during synthesis.

Solution

In the usr_rd.v/.vhd files, the sb_ecc error and db_ecc_error are not handled correctly, which causes the following errors in XST:

"ERROR:Xst:528 - Multi-source in Unit <usr_rd> on signal <sb_ecc_error[1]>; this signal is connected to multiple drivers. Drivers are:

Output port FIFO36_72_EXP:SBITERR of instance <u_ddr2_top/u_mem_if_top/u_usr_top/u_usr_rd/.gen_rdf[0].u_rdf1>
Output port FIFO36_72_EXP:SBITERR of instance <u_ddr2_top/u_mem_if_top/u_usr_top/u_usr_rd/.gen_rdf[1].u_rdf>"

"ERROR:Xst:528 - Multi-source in Unit <usr_rd> on signal <db_ecc_error[1]>; this signal is connected to multiple drivers.

Drivers are:

Output port FIFO36_72_EXP:DBITERR of instance <u_ddr2_top/u_mem_if_top/u_usr_top/u_usr_rd/.gen_rdf[0].u_rdf1>
Output port FIFO36_72_EXP:DBITERR of instance <u_ddr2_top/u_mem_if_top/u_usr_top/u_usr_rd/.gen_rdf[1].u_rdf>"

This issue is resolved in MIG v2.2, which is scheduled for release at the end of April 2008. If the updated file is needed before this time, open a WebCase and request the files associated with this Answer Record:

http://www.xilinx.com/support/clearexpress/websupport.htm

AR# 30702
Date Created 04/11/2008
Last Updated 12/15/2012
Status Active
Type General Article
Devices
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