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AR# 30704

10.1 Install - EDK Service Pack Release Notes (README)


This README Answer Record contains the Release Notes for 10.1 Service Packs.

The Release Notes include installation instructions and a list of the issues that have been fixed.

EDK Service Packs are cumulative (for example, fixes in Service Pack 1 are also included in Service Pack 2).

Note: EDK 10.1 sp1 requires ISE 10.1 sp1 or later.


A successful installation of Xilinx EDK 10.1 Service Pack "x" updates your software version number to 10.1.0xi.

  • The destination directory specified during the setup operation must contain an existing Xilinx EDK installation.
    Only existing files are updated.
  • You must set the Xilinx and Xilinx_EDK environment variables before installing the Service Pack.

Installation Instructions for Windows Users

1. Download the EDK_10_1_0xi_win.exe file at:


2. Run the EDK_10_1_0xi_win.exe file.

Installation Instructions for Red Hat Linux and Solaris Users

1. Download the EDK_10_1_0xi_<platform>.zip file at:


2. Move the .zip file to an empty "staging" area and unzip the downloaded file.

For Example:

mv EDK_10_1_0xi_<platform>.zip /home/<staging_dir>
cd /home/<staging_dir>
unzip EDK_10_1_0xi_<platform>.zip

3. Run setup.

Issues Fixed by 10.1 Service Pack 1

(Xilinx Answer 30799) 10.1 EDK - How do I install a patch for the Processor IP Core in EDK tools?
(Xilinx Answer 30830) 10.1 EDK SP1, plbv46_pcie_v2_01_a - When using Base System Builder to build a Virtex5_FXT system, the plbv46_pcie core fails timing
(Xilinx Answer 30831) 10.1 EDK SP1 - xps_ll_temac_v1_01_a, there currently is no TCL/DRC to ensure between the PHY type and PORTs used
(Xilinx Answer 30833) 10.1 EDK SP1, ppc440mc_ddr2_v1_01_a - Incorrect port width setting in MPD file for 16-bit and 32-bit memory interfaces
(Xilinx Answer 30188) 10.1 EDK and EDK 10.1 SP1, xps_ll_temac_v1_01_a - Pause Packets when enabled cause the TEMAC to reject the packet as "bad" and any valid packet that follows is being rejected
(Xilinx Answer 30835) 10.1 EDK and 10.1 EDK SP1, ppc440mc_ddr2_v1_00_a, ppc440mc_ddr2_v1_01_a - Incorrect write data during write transactions, under certain voltage and temperature conditions
(Xilinx Answer 30706) 10.1 EDK - "ERROR:Xst:1617 - Processing TIMESPEC TS_ASYNC_FIFO_ccx2mb_0_to_microblaze_0: user TIMEGRP..."
(Xilinx Answer 30707) 10.1 EDK - "ERROR:MDT - PARAMETER C_NUM_OFFCHIP_SS_BITS has value 5 which does not fall ..."
(Xilinx Answer 30708) 10.1 EDK - Clock Generator is not producing a clock with the desired clock frequencies
(Xilinx Answer 30709) 10.1 EDK - "ERROR:LIT:141 - CLK90, CLK270, CLK2X and CLK2X180 of DCM symbol DCM_INST"
(Xilinx Answer 30710) 10.1 EDK - "ERROR:MDT - Failed to load XMP File"
(Xilinx Answer 30711) 10.1 EDK - "** Error: (vsim-8346) xps_most_nic.vhd(565)"
(Xilinx Answer 30712) 10.1 EDK - "** Error: (vsim-8346) xps_usb2_device.vhd(426)"
(Xilinx Answer 30298) 10.1 EDK - After running compedklib to create simulation libraries for NCSim, I cannot run simulations
(Xilinx Answer 30773) 10.1 EDK - "** Error: (vsim-8346) mpmc_ctrl_if.vhd(499): VHDL component port was not found because Verilog port 'MPMC_Clk' was mapped to the extended identifier '\MPMC_Clk\'"
(Xilinx Answer 30550) 10.1 EDK - When I connect with GDB to PPC440, an error occurs: "Error: No Data on the Socket"
(Xilinx Answer 30774) 10.1 EDK - Clock Generator uses an unnecessary DCM
(Xilinx Answer 30040) 10.1 EDK - Create/Import Peripheral (CIP) Wizard's ISE project is empty
(Xilinx Answer 30776) 10.1 EDK - SDK cannot download ppc_bootloop.elf when targeting the PPC440
(Xilinx Answer 30777) 10.1 EDK - Linux 2.6 MLD v1.00c does not enable lltemac support properly
(Xilinx Answer 29791) 10.1 EDK - TEMAC and Ethernet Lite issues addressed
(Xilinx Answer 30274) 10.1 EDK - Downloading a VxWorks image for PPC440 does not work
(Xilinx Answer 30456) 10.1 EDK - "ERROR:MDT - Error while performing Cygwin checks..."
(Xilinx Answer 30402) 10.1 EDK - XMD -cable Xilinx_platformusb does not connect when using the USB download cable
(Xilinx Answer 30778) 10.1 EDK - "ERROR: Could not find BestRun in system_xplorer.rpt"
(Xilinx Answer 30271) 10.1 EDK - GCC Error: "/cygdrive/c/Temp/ccIhdfRf.s:20: Error: Variable is accessed using small data read write anchor, but it is not in the small data read write section"

Fixed in MPMC v4.01.a

(Xilinx Answer 30459) 9.2i EDK, MPMC v3.00b - MPMC does not correct assert CS_n in dual-DIMM setups
(Xilinx Answer 29993) 9.2i EDK, MPMC v3.00b - How do I create a dual-rank/dual-DIMM MPMC design? What are the limitations that will cause it to fail?
(Xilinx Answer 30454) 9.2i EDK, MPMC v3.00b - Global Cycle counter in Performance Monitor counts on incorrect clock
(Xilinx Answer 30379) 10.1 EDK, MPMC v4.00.a - "ERROR:MDT..Auto-computed high address overflows the 32-bit address space"
(Xilinx Answer 30334) 10.1 EDK, MPMC v4.00.a - Cannot find MIG /mig21/user_design/rtl/mig21.v for Virtex-5 DDR2 design
(Xilinx Answer 29261) 10.1 EDK, MPMC v4.00.a - How do I rev up a Virtex-5 DDR2 MPMC v3 design to MPMC v4?
(Xilinx Answer 23560) 10.1 EDK, MPMC v4.00.a - Error "cp: copying multiple files, but last argument `system_v4.ucf.tmp3' is not a directory"
(Xilinx Answer 30206) 10.1 EDK, MPMC v4.00.a - Data sheet documentation for PIM<Port_Num>_RdModWr is incorrect
(Xilinx Answer 30234) 10.1 EDK, MPMC v4.00.a - Refreshes are not performed during calibration of second-rank
(Xilinx Answer 30330) 10.1 EDK, MPMC v4.00.a - MPMC SDMA timing diagrams are incorrect
(Xilinx Answer 30132) 10.1 EDK, MPMC v4.00.a - Error: "mpmc_ecc_example.c:318: error: InterruptController undeclared"
(Xilinx Answer 30133) 10.1 EDK, MPMC v4.00.a - NPI PIM_RdFifo_Empty signal incorrectly goes Low when PIM_RdFifo_Flush is asserted
(Xilinx Answer 29852) 10.1 EDK, MPMC v4.00.a - Memory details in MPMC GUI are not updating on CUSTOM part choice

Issues Fixed by 10.1 Service Pack 2

(Xilinx Answer 30967) 10.1 EDK - Base System Builder (BSB) does not configure a soft core TEMAC properly
(Xilinx Answer 30968) 10.1 EDK - Base System Builder (BSB) does not properly connect a second MPMC for a DDR2
(Xilinx Answer 30324) 10.1 EDK - PHY interrupt input pin does not get connected in Base System Builder (BSB) for the ML410
(Xilinx Answer 30669) 10.1 EDK - USB connected mass storage device does not appear as a drive on my embedded Linux project
(Xilinx Answer 30974) 10.1 EDK - Why am I not able to select to initialize my block RAMs in a dual processor system?
(Xilinx Answer 30685) 10.1 EDK - Why is the IP Catalog empty when Virtex-5 FXT devices are selected?
(Xilinx Answer 30643) 10.1 EDK - "ERROR:: Cannot locate library chipscope_plbv46_iba_v1_01_a"
(Xilinx Answer 30642) 10.1 EDK - Why does the chipscope_icon_v1.02a use BUFGs even though I set use_bufg = false?
(Xilinx Answer 30225) 10.1 EDK - LibGen gives me errors in _profile_timer_hw.c when I try to profile for the PPC440
(Xilinx Answer 30155) 10.1 EDK - How do I initialize the network interface for lwIP 3.00.a?
(Xilinx Answer 25025) 10.1 EDK - My design does not work if the .vectors section is allocated in IOCM
(Xilinx Answer 30708) 10.1 EDK - Clock Generator is not producing a clock with the desired clock frequencies
(Xilinx Answer 31061) 10.1 EDK - The MPMC v4 Configure IP GUI does not display correct DQS and DM values for device
(Xilinx Answer 30960) 10.1 EDK - "WARNING:MDT - The value for the parameter clock_generator_0:C_DCM0_CLKIN_PERIOD - is not specified in MHS"
(Xilinx Answer 30890) 10.1 EDK - Clock Generator version 2.01.a does not output clock signals during simulation
(Xilinx Answer 30979) 10.1 EDK - My Ethernet with lwIP stops responding after printing out the message "Rx packet rejected"
(Xilinx Answer 31180) 10.1 EDK - BSB creates incorrect address for the Spartan-3A Starter Kit
(Xilinx Answer 30898) 10.1 EDK - PLBv46 Master Burst v1.00a - incorrect data read back for every odd word address
(Xilinx Answer 30967) 10.1 EDK - Platgen errors out when ppc440_mc_ddr2 DWIDTH is less than 64-bits
(Xilinx Answer 30834) 10.1 EDK SP2 - xps_ll_temac_v1_01_a, any valid packet that follows the pause packet is being rejected by the temac
(Xilinx Answer 31182) 10.1 EDK SP2, xps_can_v1_00_a - Data sheet indicates supported in the Virtex-4 devices. However, it is not listed in the 'mpd' as supported
(Xilinx Answer 31187) 10.1 EDK SP2 - spi_v1_12_a driver support is missing in linux_2_6_v1_01_b MLD
(Xilinx Answer 31188) 10.1 EDK SP2, microblaze_v7_10_b - Linux can crash or freeze MicroBlaze when stopping and continuing in the debugger
(Xilinx Answer 31189) 10.1 EDK SP2, microblaze_v7_10_b - WhenC_DCACHE_ALWAYS_USED = 1, the old contents in the data cache can cause MicroBlaze to hang
(Xilinx Answer 31190) 10.1 EDK SP2, xps_ll_temac_v1_01_a - With SGMII, when using the 125 MHz ref clock for the MGT in Virtex-4, the MGT PLL does not lock
(Xilinx Answer 31191) 10.1 EDK SP2, xps_ethernetlite_v2_00_a - Missing Virtex-II Pro support in bdd
(Xilinx Answer 31193) 10.1 EDK SP2, ppc440mc_ddr2_v1_01_a - Major version number change due to MPD file update
(Xilinx Answer 31179) 10.1EDK SP2, apu_fpu_virtex5_v1_00_a - Enabling FPU Exceptions could cause Data Corruption or Processor Hang
(Xilinx Answer 31181) 10.1 EDK SP2, apu_fpu_virtex5_v1_00_a - XST synthesis errors out when C_USE_RLOCS=1, in high-performance FPU variant

Fixed in MPMC v4.02.a

(Xilinx Answer 29737) 9.2i EDK, MPMC v3.00a - What is the expected performance of MPMC?
(Xilinx Answer 30899) 10.1 EDK, MPMC v4.01.a - "ERROR:ConstraintSystem:58 - Constraint... does not match any design objects""
(Xilinx Answer 30904) 10.1 EDK, MPMC v4.00.a - NPI accesses do not access the correct address when C_PIM<Port_Num>_OFFSET is used
(Xilinx Answer 30819) 10.1 EDK, MPMC v4.01.a - ECC access does not obey NPI_RdModWr signal
(Xilinx Answer 30921) 10.1 EDK, MPMC v4.01.a - "MPMC_Idelayctrl_Rdy_O signal does not include MPMC_Idelayctrl_Rdy_I signal"
(Xilinx Answer 30922) 10.1 EDK, MPMC v4.01.a - PLB PIMs do not function correctly when control ports are used
(Xilinx Answer 30926) 10.1 EDK, MPMC v4.01.a - MPMC block RAM write FIFOs corrupt data after 2x 64-word occupancy
(Xilinx Answer 30836) 10.1 EDK, MPMC v4.01.a - SDMA control ports are not functioning correctly
(Xilinx Answer 30773) 10.1 EDK - "** Error: (vsim-8346) mpmc_ctrl_if.vhd(499): VHDL component port was not found because Verilog port "MPMC_Clk" was mapped to the extended identifier "\MPMC_Clk\""
(Xilinx Answer 30925) 10.1 EDK, MPMC v4.01.a - MPMC C_SIM_SKIP_INIT always is active, violating DDR/DDR2 200us initialization time
(Xilinx Answer 30924) 10.1 EDK, MPMC 3.00.b - "ERROR:MDT - mpmc_v2_1_0.mpd Value of parameter C_MEM_REDUCED_DRV of type std_logic_vector must start with prefix 0x or 0b"
(Xilinx Answer 31208) 10.1 EDK, MPMC v4.00.a - Spartan-3 BSB designs have difficulty meeting timing

Issues Fixed by 10.1 Service Pack 3

(Xilinx Answer 31227) 10.1 EDK - Platgen error "The connection to port jtgc405tdi0 on JTAGPPC_CNTLR is single-ended"
(Xilinx Answer 31222) 10.1 EDK - Base System Builder (BSB)-generated TestApp_Peripheral for ML507 fails when data section is placed in DDR2 memory
(Xilinx Answer 31560) 10.1 EDK - "ERROR:MDT - C_MEM_CAS_LATENCY0 (mpmc) - Error: No suitable CAS latency found for the Clock Frequency: 125.0 MHz"
(Xilinx Answer 31067) 10.1 EDK - Using G++ (C++) for PowerPC 440 gives the error "undefined reference to `XCache_EnableICache(unsigned int)"
(Xilinx Answer 31192) 10.1 EDK - Why does the soft multiplier function get used in the Spartan-3A DSP part, even though I am using mul32 in MicroBlaze?
(Xilinx Answer 31278) 10.1 EDK - Why does image creation fail for PetaLinux and BlueCat after installing Service Pack 2?
(Xilinx Answer 31559) 10.1 EDK - Why do I not get any time data when profiling on a MicroBlaze system?
(Xilinx Answer 31441) 10.1 EDK - Why does the lwIP library always assume that I will be using my first PHY?
(Xilinx Answer 30889) 10.1 EDK - USB connected mass storage device does not appear as a drive on my embedded VxWorks project
(Xilinx Answer 31259) 10.1 EDK - "FATAL_ERROR:GuiUtilities:Gq_Application.c:590:1.20"
(Xilinx Answer 31374) 10.1 EDK - Launching an Xbash shell from DOS intermixes the DOS prompt with the bash prompt
(Xilinx Answer 31238) 10.1 EDK - XMD error when using EDK User Repository for custom pcores
(Xilinx Answer 31565) 10.1 EDK - XMD gives a segmentation fault
(Xilinx Answer 31621) 10.1 EDK - Why am I unable to regenerate my EDK system after making modifications to the ChipScope core?
(Xilinx Answer 31656) 10.1 EDK - The agilent_atc2 core cannot find the ChipScope installation
(Xilinx Answer 31688) 10.1 EDK SP3, xps_most_nic_v1_00_b - This latest core has added the PLL monitoring Logic to identify false PLL locks and issue an external reset to IDT External PLL
(Xilinx Answer 31182) 10.1 EDK SP2, xps_can_v1_00_a - The data sheet indicates "supported" in the Virtex-4 devices. However, it is not listed in the "mpd" as supported
(Xilinx Answer 31532) 10.1 EDK SP3, plbv46_pcie v3.00.a - The latest "plbv46_pcie v3.00.a" core fixes many issues with PLBv46_PCIe bridge versions v1.00.a, v2.00.a, v2.01.a and v2.01.b
(Xilinx Answer 31431) 10.1EDK SP3, plbv46_pcie_v3_00_a - Un-encrypt (VHDL/Verilog) source code for plbv46 PCIe bridge
(Xilinx Answer 31446) 10.1 EDK, ppc440mc_ddr2 - How do I use the ppc440mc_ddr2 signal MI_MCCLKDIV2?
(Xilinx Answer 31447) 10.1 EDK, ppc440mc_ddr2 - Does the MI_MCRESET signal need to be an external input?
(Xilinx Answer 31695) 10.1 EDK SP3, xps_ethernetlite_v2_00_b - This latest tactical patch supports the Virtex-4 Q and Virtex-4 QR devices and fix the postPar simulation
(Xilinx Answer 31700) 10.1 EDK SP3, xps_ll_fifo_v1_01_a - This latest version fixed the issue with the XPS LL FIFO incorrectly interpreting data
(Xilinx Answer 30919) 10.1 EDK - SysMon_v1_00_a - SysMon SW driver for xps_sysmon_adc_v1_00_a does not enable multiple Calibration Enables.
(Xilinx Answer 31241) 10.1 EDK, XPS LL TEMAC v1.01a - In RGMII mode, Transmit data are driven on the rising edge
(Xilinx Answer 31253) 10.1 EDK, MPMC v4.00.a - "WARNING:ParHelpers:198 - One or more "EXACT" mode Directed Routing... not successfully routed"
(Xilinx Answer 30134) 10.1 EDK, MPMC v4.00.a - How do I revup a design with multiple MPMCv3 MIG cores to MPMCv4?
(Xilinx Answer 31445) 10.1 EDK, MPMC v4.00.a - ncelab: *F,CUMSTS: Timescale directive missing on one or more modules
(Xilinx Answer 31268) 10.1 EDK, MPMC v4.01.a - MPMC hangs when read path FIFOs disabled
(Xilinx Answer 31443) 10.1 EDK, MPMC v4.00.a - ERROR:ConstraintSystem:58 - Constraint <INST...data_tap_inc_1*" AREA_GROUP=data_tap_gp1;> does not match any design objects
(Xilinx Answer 31444) 10.1 EDK, MPMC v4.00.a - MPMC calibration fails in simulation with Virtex-4 DDR/DDR2 PHY
(Xilinx Answer 31286) 10.1 EDK, MPMC v4.02.a - "ERROR:ConstraintSystem:58 - Constraint does not match any design objects"
(Xilinx Answer 30933) 10.1 EDK, MPMC v4.01.a - DM-Pins always High and DQ incorrect on writes when using SDR SDRAM PHY
(Xilinx Answer 31159) 10.1 EDK, MPMC v4.00.a - Chipselect (CS) asserted too late on Spartan-3 for successful precharge
(Xilinx Answer 31157) 10.1 EDK, MPMC v4.00.a - What are other PMCLR register values? How do I clear the dead and global cycle counters?
AR# 30704
Date Created 04/14/2008
Last Updated 06/10/2015
Status Active
Type General Article
  • EDK - 10.1 sp2
  • EDK - 10.1
  • EDK - 10.1 sp1
  • EDK - 10.1 sp3