When I create a Base System Builder design (BSB) for the ML310, the following MAP error occurs:"
"ERROR:LIT:141 - CLK90, CLK270, CLK2X and CLK2X180 of DCM symbol
"clock_generator_0/clock_generator_0/clkgen_core_inst/clkgen_arch_inst/using_
dcm_arch_model.dcm_array[1].using_dcm_module_inst.dcm_module_inst/Using_Virte
x.DCM_INST" (output
signal=clock_generator_0/clock_generator_0/clkgen_core_inst/clkgen_arch_inst/
using_dcm_arch_model.dcm_array[1].using_dcm_module_inst.dcm_module_inst/CLK0_
BUF) is not available when DLL_FREQUENCY_MODE is set to HIGH.
Errors found during logical drc."
This problem has been fixed in the latest EDK 10.1 Service Pack, available at:
http://www.xilinx.com/xlnx/xil_sw_updates_home.jsp
The first service pack containing the fix is EDK 10.1 Service Pack 1.