^

AR# 30773 10.1 EDK - "** Error: (vsim-8346) mpmc_ctrl_if.vhd(499): VHDL component port was not found because Verilog port "MPMC_Clk" was mapped to the extended identifier "\MPMC_Clk\""

When I simulate an embedded system that contains a static phy with the MPMC, the following errors occur in ModelSim:

"# ** Error: (vsim-8346) C:/EDK/hw/XilinxProcessorIPLib/pcores/mpmc_v3_00_b/hdl/vhdl/mpmc_ctrl_if.vhd(499): VHDL component port was not found because Verilog port 'MPMC_Clk' was

# mapped to the extended identifier '\MPMC_Clk\'.

# Region: /system/ddr_sdram_16mx16/DDR_SDRAM_16Mx16/mpmc_ctrl_inst/mpmc_ctrl_if_0/mpmc_ctrl_logic_0

# ** Error: (vsim-8346) C:/EDK/hw/XilinxProcessorIPLib/pcores/mpmc_v3_00_b/hdl/vhdl/mpmc_ctrl_if.vhd(499): VHDL component port was not found because Verilog port 'ECC_Reg_Out' was

# mapped to the extended identifier '\ECC_Reg_Out\'.

# Region: /system/ddr_sdram_16mx16/DDR_SDRAM_16Mx16/mpmc_ctrl_inst/mpmc_ctrl_if_0/mpmc_ctrl_logic_0

# ** Error: (vsim-8346) C:/EDK/hw/XilinxProcessorIPLib/pcores/mpmc_v3_00_b/hdl/vhdl/mpmc_ctrl_if.vhd(499): VHDL component port was not found because Verilog port 'Static_Phy_Reg_Out' was

# mapped to the extended identifier '\Static_Phy_Reg_Out\'.

# Region: /system/ddr_sdram_16mx16/DDR_SDRAM_16Mx16/mpmc_ctrl_inst/mpmc_ctrl_if_0/mpmc_ctrl_logic_0

# ** Error: (vsim-8346) C:/EDK/hw/XilinxProcessorIPLib/pcores/mpmc_v3_00_b/hdl/vhdl/mpmc_ctrl_if.vhd(499): VHDL component port was not found because Verilog port 'Debug_Ctrl_Reg_Out' was

# mapped to the extended identifier '\Debug_Ctrl_Reg_Out\'.

# Region: /system/ddr_sdram_16mx16/DDR_SDRAM_16Mx16/mpmc_ctrl_inst/mpmc_ctrl_if_0/mpmc_ctrl_logic_0

# ** Error: (vsim-8346) C:/EDK/hw/XilinxProcessorIPLib/pcores/mpmc_v3_00_b/hdl/vhdl/mpmc_ctrl_if.vhd(499): VHDL component port was not found because Verilog port 'PM_Ctrl_Reg_Out' was

# mapped to the extended identifier '\PM_Ctrl_Reg_Out\'.

# Region: /system/ddr_sdram_16mx16/DDR_SDRAM_16Mx16/mpmc_ctrl_inst/mpmc_ctrl_if_0/mpmc_ctrl_logic_0

# ** Error: (vsim-8346) C:/EDK/hw/XilinxProcessorIPLib/pcores/mpmc_v3_00_b/hdl/vhdl/mpmc_ctrl_if.vhd(499): VHDL component port was not found because Verilog port 'PM_Data_Out' was

# mapped to the extended identifier '\PM_Data_Out\'.

# Region: /system/ddr_sdram_16mx16/DDR_SDRAM_16Mx16/mpmc_ctrl_inst/mpmc_ctrl_if_0/mpmc_ctrl_logic_0

# ** Error: (vsim-8346) C:/EDK/hw/XilinxProcessorIPLib/pcores/mpmc_v3_00_b/hdl/vhdl/mpmc_ctrl_if.vhd(499): VHDL component port was not found because Verilog port 'Bus2IP_Clk' was

# mapped to the extended identifier '\Bus2IP_Clk\'.

# Region: /system/ddr_sdram_16mx16/DDR_SDRAM_16Mx16/mpmc_ctrl_inst/mpmc_ctrl_if_0/mpmc_ctrl_logic_0

# ** Error: (vsim-8346) C:/EDK/hw/XilinxProcessorIPLib/pcores/mpmc_v3_00_b/hdl/vhdl/mpmc_ctrl_if.vhd(499): VHDL component port was not found because Verilog port 'Bus2IP_Reset' was

# mapped to the extended identifier '\Bus2IP_Reset\'.

# Region: /system/ddr_sdram_16mx16/DDR_SDRAM_16Mx16/mpmc_ctrl_inst/mpmc_ctrl_if_0/mpmc_ctrl_logic_0

# ** Error: (vsim-8346) C:/EDK/hw/XilinxProcessorIPLib/pcores/mpmc_v3_00_b/hdl/vhdl/mpmc_ctrl_if.vhd(499): VHDL component port was not found because Verilog port 'Bus2IP_Addr' was

# mapped to the extended identifier '\Bus2IP_Addr\'.

# Region: /system/ddr_sdram_16mx16/DDR_SDRAM_16Mx16/mpmc_ctrl_inst/mpmc_ctrl_if_0/mpmc_ctrl_logic_0

# ** Error: (vsim-8346) C:/EDK/hw/XilinxProcessorIPLib/pcores/mpmc_v3_00_b/hdl/vhdl/mpmc_ctrl_if.vhd(499): VHDL component port was not found because Verilog port 'Bus2IP_CS' was

# mapped to the extended identifier '\Bus2IP_CS\'.

# Region: /system/ddr_sdram_16mx16/DDR_SDRAM_16Mx16/mpmc_ctrl_inst/mpmc_ctrl_if_0/mpmc_ctrl_logic_0"

This problem has been fixed in the latest EDK 10.1 Service Pack, available at:

http://www.xilinx.com/xlnx/xil_sw_updates_home.jsp
The first service pack containing the fix is EDK 10.1 Service Pack 1.

AR# 30773
Date Created 04/14/2008
Last Updated 12/15/2012
Status Active
Type General Article