We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 30785

MIG v2.2 - Using the Update UCF feature for a QDRII x36 design requires manual modifications


When uploading a UCF and ".prj" file from a MIG v1.73/v2.0 QDRII x36 memory part design, the generated design contains the parameter "MASTERBANK_WIDTH" set to "0". 

This causes the design to fail during synthesis with the following error: 

 ERROR:HDLCompilers:55 - "../synth/../rtl/qdrii_sram.v" line 192 Bit-select of scalar wire 'masterbank_sel_pin' is illegal


MIG v1.73 used a different algorithm to generate x36 part designs. 

In this algorithm, one set of 18 bits of data (Q) and the corresponding CQ were allocated into one bank, and the other set of 18 bits of data (Q) and the corresponding CQ# were allocated into the other bank. 

Consequently, the DCI Cascade feature was not required. 

Starting in MIG v2.0, x36 part designs are generated by allocating all 36 bits of data (Q) and the corresponding CQ and CQ# into one single bank. 

As a result, the DCI Cascade feature is needed. 


MIG v1.73 


When a UCF and ".prj" file from a MIG v1.73 x36 memory part design are passed to update the UCF and generate the design, the Master Bank information is not provided. 

Consequently, the generated design ".rtl" (design top file) has the parameter MASTERBANK_WIDTH value as "0". 


To work around this issue, comment out the logic/ports related to the Master Bank. 

These include the top-level parameter, MASTERBANK_WIDTH, and the top-level input pin, masterbank_sel_pin. 


MIG v2.0 


Although the MIG v2.0 ".prj" file has the DCI_Cascade enabled, it does not contain the Master Bank information.

To work around this issue, the following must be completed: 

1. The number of Master Banks selected is represented by the parameter "MASTERBANK_WIDTH" in the design top ".rtl" file. 

Edit this parameter accordingly.  

2. The design top-level ".rtl" must include the input pin masterbank_sel_pin in the port list: 

input [MASTERBANK_WIDTH-1:0] masterbank_sel_pin; -- verilog 
masterbank_sel_pin : in std_logic_vector(MASTERBANK_WIDTH-1 downto 0); -- VHDL; 

3. The updated ".ucf" must include the DCI_Cascade syntax and the correct LOC for the input pin, masterbank_sel_pin. 


This issue is resolved in MIG 2.3.

AR# 30785
Date Created 04/15/2008
Last Updated 08/28/2014
Status Active
Type General Article