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AR# 30786

MIG v2.2 - Pin allocation for the Virtex-5 QDRII x18 36-bit design is incorrect when Reserve Pins option is used


The Virtex-5 FPGA QDRII x18 36-bit design requires two Data Read banks. Each Data Read bank requires only 20 pins (18 Q, CQ and CQ#). In some cases, MIG will not generate even if sufficient pins are selected for a Data Read bank.


In some cases, when pins are reserved (up to 18) in the bank where Data Read is selected, MIG cannot allocate a full Data Read set in this bank, although there are enough pins left (20 pins) to do so. The Master Bank selection box will be disabled.  

To work around this issue, if another group of pins such as Address/Data Write are allocated in this same bank, MIG follows the bank selection guidelines, giving first preference to Data Read and properly allocating the Data Read group in the bank. The Address/Data Write signals will not fit into the bank, and will need to have additional banks selected. 

This issue is resolved in MIG v2.3.
AR# 30786
Date Created 04/16/2008
Last Updated 05/21/2014
Status Archive
Type General Article
  • Virtex-5 FXT
  • Virtex-5 LX
  • Virtex-5 LXT
  • More
  • Virtex-5 SXT
  • Virtex-5 TXT
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  • MIG