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AR# 30789

MIG v2.2 - DDR2/QDRII multi-controller design requires modification to the user testbench to have clock and reset signals for both memories

Description

When I generate a QDRII/DDR2 multi-controller design, the output testbench provided with the user_design does not have the proper clocks and resets. Manual modification is required.

Solution

MIG generates a user design that has only a clock and reset output for the memory type selected as the first controller. For example, if DDR2 memory is selected as the first controller and QDRII is selected as the second controller, the output user design only has the DDR2 clock and reset outputs for the user testbench (user application). Because the design is a multi-controller involving both QDRII and DDR2, the user design must have clocks and resets for both controllers as outputs for the user testbench (user application) to work properly.

To work around this issue, follow these steps:

1. When DDR2 is selected as the first controller, the user design top ".rtl" file has only the DDR2 clock and reset. The following changes must be made to add the QDRII clock and reset.

In the design top level ".rtl", add the following ports and assignment statements:

Verilog

output user_rst_0_tb,

output qdrii_clk0_tb,

assign user_rst_0_tb = user_rst_0;

assign qdrii_clk0_tb = qdrii_clk0;


VHDL

user_rst_0_tb : out std_logic;

qdrii_clk0_tb : out std_logic;

user_rst_0_tb <= user_rst_0;

qdrii_clk0_tb <= qdrii_clk0;


2. When QDRII is selected as the first controller, the user design top ".rtl" file has only the QDRII clock and reset. The following changes must be made to add the DDR2 clock and reset.

In the design top level ".rtl", add the following ports and assignment statements:

Verilog

output rst0_tb,

output ddr2_clk0_tb,

assign rst0_tb = rst0;

assign ddr2_clk0_tb = ddr2_clk0;


VHDL

rst0_tb : out std_logic;

ddr2_clk0_tb : out std_logic;

rst0_tb <= rst0;

ddr2_clk0_tb <= ddr2_clk0;

AR# 30789
Date Created 04/16/2008
Last Updated 12/15/2012
Status Active
Type General Article
IP
  • MIG