Description
Keywords: MCOMMA_10B_VALUE, PCOMMA_10B_VALUE, cfg_lstatus
When simulating the x4 Virtex-II Pro Core using Verilog, it trains down to a x1 link. This is indicated by looking at cfg_lstatus[9:4] when trn_lnk_up_n is asserted.
Solution
The MCOMMA_10B_VALUE and PCOMMA_10B_VALUE values are not being applied correctly in the core simulation model. The model is pci_exp_4_lane_64b_ep.v found in the directory
pci_exp_4_lane_64b_ep/v2pro/simulation/verilog.
To fix this issue, make the following modifications:
On line 18829 change:
defparam plm_mgt_GST0.MCOMMA_10B_VALUE = 10'b1100000101;
defparam plm_mgt_GST0.PCOMMA_10B_VALUE = 10'b0011111010;
GT_CUSTOM plm_mgt_GST1 (
to:
defparam plm_mgt_GST1.MCOMMA_10B_VALUE = 10'b1100000101;
defparam plm_mgt_GST1.PCOMMA_10B_VALUE = 10'b0011111010;
GT_CUSTOM plm_mgt_GST1 (
On line 18957 change:
defparam plm_mgt_GST0.MCOMMA_10B_VALUE = 10'b1100000101;
defparam plm_mgt_GST0.PCOMMA_10B_VALUE = 10'b0011111010;
GT_CUSTOM plm_mgt_GST2 (
to:
defparam plm_mgt_GST2.MCOMMA_10B_VALUE = 10'b1100000101;
defparam plm_mgt_GST2.PCOMMA_10B_VALUE = 10'b0011111010;
GT_CUSTOM plm_mgt_GST2 (
On line 19085 change:
defparam plm_mgt_GST0.MCOMMA_10B_VALUE = 10'b1100000101;
defparam plm_mgt_GST0.PCOMMA_10B_VALUE = 10'b0011111010;
GT_CUSTOM plm_mgt_GST3 (
to:
defparam plm_mgt_GST3.MCOMMA_10B_VALUE = 10'b1100000101;
defparam plm_mgt_GST3.PCOMMA_10B_VALUE = 10'b0011111010;
GT_CUSTOM plm_mgt_GST3 (
On line 18829 change:
defparam plm_mgt_GST0.MCOMMA_10B_VALUE = 10'b1100000101;
defparam plm_mgt_GST0.PCOMMA_10B_VALUE = 10'b0011111010;
GT_CUSTOM plm_mgt_GST1 (
to:
defparam plm_mgt_GST1.MCOMMA_10B_VALUE = 10'b1100000101;
defparam plm_mgt_GST1.PCOMMA_10B_VALUE = 10'b0011111010;
GT_CUSTOM plm_mgt_GST1 (
Revision History04/16/2008 - Initial Release