AR #30812 - 10.1 UniSim - DCM_SP does not lock in VHDL simulation
10.1 UniSim - DCM_SP does not lock in VHDL simulation
| AR# | 30812 |
| Part | SW-Sim Libraries |
| Last Modified | 2008-04-28 00:00:00.0 |
| Status | Active |
| Keywords | DCM, Spartan, Lock, VHDL, simulation, UniSim |
Description
Keywords: DCM, Spartan, Lock, VHDL, simulation, UniSim
DCM_SP does not lock in VHDL simulation. Why?
Solution
DCM_SP locked signal is not connected in VHDL. This is a bug in the model, and it is fixed in 10.1 Sp2.If you want a immediate fix for this model, please open a Technical Support WebCase: http://www.xilinx.com/support/clearexpress/websupport.htm
This issue is not seen by Verilog models.