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AR# 30814

MIG v2.2, Virtex-5 DDR2 - How do I simulate a MIG DDR2 controller using VCS?

Description

Currently, MIG supports simulation using ModelSim only.

To help users who need VCS to get started, this Answer Record includes a working VCS simulation with a MIG output example design and the steps to follow to run a VCS simulation.

This is not supported, but  is provided to help users that do not have access to ModelSim to run a MIG simulation using VCS.

Note: The example simulation uses a MIG v2.1 DDR2 Virtex-5 controller.

Solution

A working example of a VCS MIG simulation can be found at:

http://www.xilinx.com/txpatches/pub/applications/misc/ar30814.zip

This ZIP file contains an example MIG design (MIG v2.1 V5 DDR2), VCS script files, and a "readme.txt" file.

The "readme.txt" file provides instructions on running the VCS simulation with the included MIG design.

To use the example script files and to run a VCS simulation with a different MIG design example or a user design, complete the following steps:
 

1. Compile the top-level testbench (sim_tb_top.v) with VCS to identify if labels are required on the "for loop" statements.

The VCS parser might flag an error (depending on the version of VCS) referencing the memory model instantiations.

This occurs because the "for loop" statement does not contain a label.

Certain versions of VCS require that each "for loop" contain a label as follows:

for(i = 0; i < DQS_WIDTH/2; i = i+1) begin:label_1

If compilation fails, add labels to each "for loop".

 

2. VCS system calls are also required in the top-level testbench (sim_tb_top.v).

The following syntax must be added:

'ifdef VCS //Synopsys VPD dump 

VCS is defined in the simulation script shown below:

$vcdplusfile("mig_sim.vpd");

$vcdpluson;

$vcdplusglitchon;

$vcdplusflush;

'endif

 

3. Copy the "simulate_mig.sh", "board_rtl.f", and "Xilinx_lib_vcs.f" script files provided in the above archive into the MIG output "sim" directory.

 

4. In "Xilinx_lib_vcs.f", edit the pointers to the UNISIM and SIMPRIM paths so that they correctly map to the simulation models.

 

5. In "board_rtl.f", change the defines so that they match the component configuration. 

The controller RTL paths are relative and should be mapped correctly, as long as the directory hierarchy has not changed from the default output of MIG. 

If the hierarchy has changed, then change these path references accordingly.

 

6. Type "source simulate_mig.sh" to run the script.

This outputs the "simv" executable file.

The text below shows the example simulation script:

#!/bin/sh
#

# MIG VCS Run Script

#

/bin/rm -rf *.daidir

/bin/rm -rf simv*

/bin/rm -rf csrc

vcs +v2k +cli +define+VCS \

-PP \

-f Xilinx_lib_vcs.f \

-f board_rtl.f

"Xilinx_lib_vcs.f" contains pointers to the Xilinx UniSim and SimPrim libraries and might need to be changed depending on the location of the simulation models:
 

-y $Xilinx/verilog/src/simprims
-y $Xilinx/verilog/src/unisims+libext+.v+


"board_rtl.f" contains pointers to the MIG controller RTL to be compiled. 

The defines at the top of this file are used by the generic memory model.

Edits to these defines are required and must be set to match the memory component configuration selected in MIG.

Note: Do not compile black_box.v when simulating the controller.

This file is used by Synplify during design synthesis.

If the file is compiled, the calibration fails during stage 3 (as seen on the calib_err[3:0] signal).

"board_rtl.f" contains pointers to the MIG controller RTL to be compiled. 

The defines at the top of this file are used by the generic memory model.

Edits to these defines are required and must be set to match the memory component configuration selected in MIG.

Do not compile black_box.v when simulating the controller.

This file is used by Synplify during design synthesis.

If the file is compiled, the calibration fails during stage 3 (as seen on the calib_err[3:0] signal).


+define+x256Mb

+define+sg3+define+x8

+incdir+.

+incdir+../rtl

// MIG Test Bench and Memory Model

//---------------------------------

ddr2_model.v

glbl.v

sim_tb_top.v

// MIG Controller RTL

//--------------------------------

../rtl/chipscope.v

../rtl/ctrl.v

../rtl/ddr2_sdram.v

../rtl/ddr2_top.v

../rtl/idelay_ctrl.v

../rtl/infrastructure.v

../rtl/mem_if_top.v

../rtl/phy_calib.v

../rtl/phy_ctl_io.v

../rtl/phy_dm_iob.v

../rtl/phy_dq_iob.v

../rtl/phy_dqs_iob.v

../rtl/phy_init.v

../rtl/phy_io.v

../rtl/phy_top.v

../rtl/phy_write.v

../rtl/tb_test_addr_gen.v

../rtl/tb_test_cmp.v

../rtl/tb_test_data_gen.v

../rtl/tb_test_gen.v

../rtl/tb_top.v

../rtl/usr_addr_fifo.v

../rtl/usr_rd.v

../rtl/usr_top.v

../rtl/usr_wr.v

 
7. Type "simv" to run the simulation.

A VCS ".vpd" file is created that can be opened in the VCS simulation GUI.

These modifications have been added to the MIG 2.3 design.

AR# 30814
Date Created 04/23/2008
Last Updated 03/31/2015
Status Active
Type General Article
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