UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 30835

10.1 EDK, ppc440mc_ddr2 - Incorrect write data during write transactions, under certain voltage and temperature conditions

Description

The patch included in the resolution addresses the following issues in EDK 10.1 and EDK 10.1.01 (sp1), affecting only the ppc440mc_ddr2_v1_00_a and ppc440mc_ddr2_v1_01_a cores:

- Under worse case conditions, write errors were observed. A fix for this issue is implemented in the latest core.

- Incorrect functionality was observed in the ECC mode with Burst Length 8. A fix for this issue is included in this latest core.

- In addition, the ppc440mc_ddr2_v2_1_0.MPD file has been fixed to address 16-bit and 32-bit memory Interface.

NOTE: To use this patch, you need EDK 10.1 Service Pack 1.

The latest version of the Memory Controller data sheet for ppc440mc_ddr2_v1_02_a is located at:

http://www.xilinx.com/txpatches/pub/applications/misc/ppc440mc_ddr2.pdf

Solution

These issues have been corrected with the latest ppc440mc_ddr2_v1_02_a core.

A patch can be downloaded from the following link:

http://www.xilinx.com/txpatches/pub/applications/refdes/ppc440mc_ddr2_v1_02_a.zip

The latest patch has a Date: May 08, 2008 in the Readme file.

Please unzip and place the patch only in the local pcore directory of your current project for the implementation.

- If you are revving up your current design from EDK 10.1 with this latest patch, you will need to add MI_MCCLKDIV2 port for Divide clock by 2 into the MHS. Please add the following port in the ppc440mc_ddr2 instance on your MHS,

PORT mi_mcclkdiv2 = sys_clk_s.

In this example, sys_clk_s operates at 100 MHz when the DDR2 clock is at 200 MHz.

- In addition, you will need to replace and update with the following constrains in your system.ucf file:

###############################################################

#

# NEW BRAM Location Constraints

#

###############################################################

INST "ppc440_mc_ddr2_0/*/*u_rdf" LOC = RAMB36_X0Y19;

INST "ppc440_mc_ddr2_0/*/*u_rdf1" LOC = RAMB36_X0Y18;

INST "ppc440_mc_ddr2_0/*/*gen_wdf[0]*u_wdf" LOC = RAMB36_X0Y17;

INST "ppc440_mc_ddr2_0/*/*gen_wdf[1]*u_wdf" LOC = RAMB36_X0Y16;

###############################################################

NOTE: ppc440_mc_ddr2_0 is the parameter INSTANCE in the ppc440mc_ddr2.

Currently, there is an issue with XMD when the patch is installed in the EDK_Patch_Repository (i.e., Answer Record 30799). See (Xilinx Answer 30799). Please install in the pcore as stated above.

The latest core will be released in the EDK 10.1 Service Pack 2 (sp2). EDK 10.1sp2 will be available at:

http://www.xilinx.com/xlnx/xil_sw_updates_home.jsp

AR# 30835
Date Created 04/24/2008
Last Updated 12/15/2012
Status Active
Type General Article