We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 30856

10.1 CORE Generator - ChipScope core is not created if EDIF is selected as netlist output type


CORE Generator does not produce EDIF for ChipScope cores.

If the project options in the CORE Generator GUI are set to create EDIF netlist, when creating a ChipScope core, the ".edn" file is not created.

The generation fails with the following errors:

"ERROR:sim - Error: Could not read


Finished Generating.

ERROR:sim:57 - Error found during generation"


The ChipScope core does not support EDIF output. CORE Generator should issue a warning message stating that the netlist type is not supported and an NGC file will be generated instead.

This problem has been fixed in the latest 10.1 Service Pack available at:

The first service pack containing the fix is 10.1 Service Pack 1.
AR# 30856
Date Created 04/25/2008
Last Updated 07/28/2010
Status Archive
Type General Article