UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 30873

10.1 Virtex-5 PAR - IO Placement rules changes may introduce placement failures in 10.1 sp1

Description

My design ran okay in a previous revision, but now it fails in 10.1 sp1 with one of the following placement errors. What has changed that makes my design fail?

Phase 1.1

ERROR:Place:820 - Q2TM.pcf line 71: CONFIG DCI_CASCADE = "4,6" is not a valid constraint.

ERROR:Place:311 - The IOB <IO Name> is locked to site IOB_X1Y111 in bank 2. This violates the SelectIO banking rules.

Other incompatible IOBs may be locked to the same bank, or this IOB may be illegally locked to a Vref site.

ERROR:Place:1747 - The IOB T65 is locked to site AM5 in Bank 5. This violates the SelectIO banking rules. Other incompatible IOBs may be locked to the same bank, or this IOB may be illegally locked to a VREF site. Please consult the SelectIO application node.

Solution

The "ERROR:Place:820" might be due to a package rules change that added a check for Virtex-5 to prevent using DCI_CASCADE across the CMT. This limitation is documented on page 219 of the Virtex-5 User's Guide:

http://www.xilinx.com/support/documentation/user_guides/ug190.pdf

The errors "ERROR:Place:311" and "ERROR:Place:1747" might be due to a conflict between *T_DCI IO Standards and non-T variants. In 9.2i the IO Standards were allowed in the same bank. It has since been determined that the hardware cannot support them together. Affected standards are:

HSTL_II_T_DCI

HSTL_II_T_DCI_18

SSTL18_II_T_DCI

SSTL2_II_T_DCI

For more detail information on this change, see (Xilinx Answer 31078).

AR# 30873
Date Created 04/29/2008
Last Updated 12/15/2012
Status Active
Type General Article