We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 30879

Spartan-3A - What is the Tsamp value for Spartan-3A families?


What is the setup and hold capture window value of an IOB input flip-flop (Tsamp) in a source synchronous design on the Spartan-3A device?


This Answer applies to Spartan-3A, Spartan-3AN, and Spartan-3A DSP.

The input capture sample window value is highly specific to a particular application, device, package, I/O standard, I/O placement, DCM usage, and clock buffer.

Please consult (Xilinx XAPP485): "1:7 Deserialization in Spartan-3E FPGAs at Speeds Up to 666 Mbps" for a similar discussion on an earlier family:


AR# 30879
Date Created 04/29/2008
Last Updated 12/15/2012
Status Active
Type General Article