I have a 64-bit custom master core in my design, so the PLB is a 64-bit bus. When reading back from an XPS block ram controller, the data returned from the IPIF is incorrect on every odd word address (i.e., ox4, oxC, etc). But for the even word addresses, the data look fine.
Is it a problem with the IPIF?
For designs that include the MDM core, this problem comes from the MDM core not driving bits 32-63 of the 64-bit RdDBus. This problem exists when connected to a 128-bit PLB bus as well.
This problem has been fixed in the latest 10.1 Service Pack available at:
http://www.xilinx.com/support/download/index.htm
The first service pack containing the fix is 10.1 Service Pack 2.