.
This situation occurs when ISim has encountered either a software environment or code construct that it does not know how to handle or resolve.
Common causes of this problem in ISE Design Suite 11.4 and newer are as follows:
- When attempting to disable a Verilog block using a hierarchical statement. For example,
disable Burst_man.pollingBurst;
To work around this issue, use code similar to:
->Burst_man.disable_pollingBurst;
//disable Burst_man.pollingBurst;
// A dummy event to work around ISIM issue CR 2982
event disable_pollingBurst;
always @(disable_pollingBurst)
disable pollingBurst;
Common causes of this problem in previous versions of ISE Design Suite that have been resolved in the latest update are as follows:
- Attempting to generate a SAIF dump file in Windows.
- When a declared signal is passed down through a VHDL design unit, and then through to a Verilog module of type inout.
- When driving an output formal signal from a procedure with a wait, which is called from another procedure.