We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 30921

10.1 EDK, MPMC v4.01.a - "MPMC_Idelayctrl_Rdy_O signal does not include MPMC_Idelayctrl_Rdy_I signal"


When using the MPMC_Idelayctrl_Rdy_I and MPMC_Idelayctrl_Rdy_O signals, the MPMC_Idelayctrl_Rdy_I are not reflected in the MPMC_Idelayctrl_Rdy_O output. This could result in downstream cores starting up before their IDELAYs are fully calibrated.


This issue has been fixed starting with MPMC v4.02.a, to be released in EDK 10.1, Service Pack 2.

AR# 30921
Date 05/21/2014
Status Archive
Type General Article
Page Bookmarked