We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 30931

Virtex-5 GTX RocketIO - MGTAVCC Power recommendations for unused tiles between calibration resistor and instantiated tiles


The GTX Transceivers in the Virtex-5 FXT FPGA devices use a calibration circuit to accurately determine the termination resistance for all transceivers in a column. This circuit is located in bank 112 for each device and utilizes a single reference resistor connected to MGTTREF_112. To correctly power this circuit and allow propagation of the calibration information to instantiated GTX_DUAL tiles, you need to follow certain power guidelines.


Bank 112:

The calibration resistor for the entire column is connected to this tile and is powered from MGTAVTTTX and MGTAVCC. Both of these supplies will need to be powered and MGTAVCC will need to be filtered per Table 37 of the Virtex-5 FPGA Data Sheet (DS202):


Unused tiles between bank 112 and those instantiated in a design:

Each unused tile between bank 112 and a GTX_DUAL instantiated in a design will need to have MGTAVCC powered. For example, in a Virtex-5 FX70T in an FF665 package, GTX_DUAL_X0Y4 is bank 112 and contains the calibration circuitry. If GTX_DUAL_X0Y2 is the only tile used in the design, then GTX_DUAL_X0Y3 will still need to be supplied MGTAVCC. For these intermediate tiles, MGTAVCC does not require the filtering that is otherwise necessary.

Relative Locations of GTX tiles
Relative Locations of GTX tiles

GTX_DUAL locations are sequential with X0Y0, starting at the bottom of the device and counting up X0Yn. They can be correlated to a particular bank by referring to the Package Placement Information section of the Virtex-5 FPGA RocketIO GTP Transceiver Users Guide:


AR# 30931
Date 02/08/2013
Status Active
Type General Article
Page Bookmarked