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AR# 30941

LogiCORE RapidIO v4.4 - Release Notes and Known Issues for 10.1 IP Update 2 (10.1_IP2)

Description

This Release Notes and Known Issues Answer Record is for the RapidIO v4.4, released in 10.1 IP Update 2, and contains the following information:

- General Information

- New Features

- Bug Fixes

- Known Issues

For installation instructions, general CORE Generator known issues, and design tools requirements, see the IP Release Notes Guide at: http://www.xilinx.com/support/documentation/user_guides/xtp025.pdf

Solution

New Features

- Integrated RocketIO Wizard output into Virtex-4 rocketio_wrapper module.

- VHDL support included for Virtex-5 wrapper modules.

- Addition of tresp_src_id, mresp_src_id and mresp_dst_id ports to support capture and retransmission of a request packet's original destination ID.

RESOLVED ISSUES

- Core LCSBA implementation removes 64 MB of possible addressing space.

- Version fixed: v4.4

- CR#472992 / AR#30939 - Use 10-bit mask with full 34-bit address for LCSBA intercept.

- CRC error on stalled packet

- Version fixed: v4.4

- CR#469678 / AR#30940 - Fixed condition which loaded in new CRC sequence on a stall just after sof received by PHY. This is a non-concern for Xilinx buffer users.

- Virtex-4 4x core may not come out of initialization state

- Version fixed: v4.4

- CR#474550 / AR#31146 - Modified rocketio_wrapper_v4_4x.v to wait for RX_READY from reset state machine.

- Virtex-4 4x core might intermittently train down to 1x mode

- Version fixed: v4.4

- CR#467616 / AR#30314 - Modified oplm_pcs_rst_sequence.v file supplied with the core to register asynchronous TXLOCK and RXLOCK signals.

- Maintenance RESPONSE packet has incorrect source device ID

- Version fixed: v4.4

- CR#455959 / AR#29936 - added tresp_src_id, mresp_src_id and mresp_dst_id inputs

- Re-initialization not forced following a change to Port Width Override

- Version fixed: v4.4

- CR#459427 / AR#30323 - Modified PHY Layer to detect a change in the port width override field and reinitialize when updated.

- Messaging packets providing incorrect treq_byte_count value

- Version fixed: v4.4

- CR#467116 / AR#30320 - Modified Logical Layer to properly decode Messaging size field. Modified testbench to properly check byte count for messaging type packets.

- 8-bit SWrite transactions using 16-bit deviceIDs suffer lost eofs

- Version fixed: v4.4

- CR#467668 / AR#30322 - Modified Logical Layer to properly forward eof through the pipeline.

- Some Logical Layer CARs are not being set correctly in the core.

- Version fixed: v4.4

- CR#458414 / AR#30054 - The following Logical Layer CARs are not being set correctly in the core:

- Assembly Information CAR (offset 0xC) - ExtendedFeaturesPtr portion

- Processing Element Features CAR (offset 0x10)

- Switch Port Information CAR (offset 0x14)

- Destination Operations CAR (offset 0x1C)

- Switch Route Table Destination ID Limit CAR (offset 0x34)

Known Issues in v4.4

The following are known issues for v4.4 of this core at the time of release:

- Virtex-4, Virtex-5 LXT/SXT, and Virtex-5 FXT core configurations are unable to traindown to x1 mode in Lane 2.

- Version to be fixed: Fix Not Scheduled

- CR#457109 / AR#30023 - Traindown in Lane 0 works successfully but the Virtex-4, Virtex-5 LXT/SXT, and Virtex-5 FXT configurations are unable to traindown in Lane 2. The RocketIO transceivers only allow traindown to the channel bonding master.

- Core reinitialization during error recovery causes recoverable protocol error.

- Version to be fixed: Fix Not Scheduled

- CR#457885 / AR#30021 - This is a corner condition that could occur if core is forced to reinitialize (i.e., - force_reinit) while it is in the process of error recovery. If this condition occurs, packets will be sent during recovery's quiet period. This situation is recoverable.

- Post-Synplicity synthesis implementation runs might exhibit ucf failures

- Version to be fixed: Fix Not Scheduled

- CR#447782 / AR#29522 - Synplicity generated net names are not consistent with XST generated names and might not be consistent between core types. The .ucf file must be edited in these failure cases.

- PNA cause field might occasionally reflect a reserved value

- Version to be fixed: Fix Not Scheduled

- CR#436767 / AR#24982 - The cause field is for debug purposes only and will not affect functionality. Occurrence is rare and requires alignment of multiple control symbols.

- Control Symbols might be lost on reinit

- Version to be fixed: Fix Not Scheduled

- CR#436768 / AR#24970 - This is an unusual and ultimately recoverable error. Set the "Additional Link Request Before Fatal" value on the Physical Configuration page of the GUI to "4" in order to prevent a lost Link Request or Link Response from causing the core to enter the port error state.

- Logical Rx does not support core side stalls

- Version to be fixed: Fix Not Scheduled

- CR#436770 / AR#24968 - The rx buffer must provide packets to the logical layer without buffer induced stall cycles. The buffer reference design provided with the core is a store and forward buffer and complies with this rule.

Known Issues in v4.3

Serial Rapid I/O v4.3 is now obsolete; you must upgrade to the latest core available through the latest IP Update. For existing known issues in Serial Rapid I/O v4.3, see (Xilinx Answer 30059).

Known Issues in v4.2

Serial Rapid I/O v4.2 is now obsolete; you must upgrade to the latest core available through the latest IP Update. For existing known issues in Serial Rapid I/O v4.2, see (Xilinx Answer 25462).

Known Issues in v4.1

Serial Rapid I/O v4.1 is now obsolete; you must upgrade to the latest core available through the latest IP Update. For existing known issues in Serial Rapid I/O v4.1, see (Xilinx Answer 23850).

Known Issues in v3.1

Serial Rapid I/O v3.1 is now obsolete; you must upgrade to the latest core available through the latest IP Update. For existing known issues in Serial Rapid I/O v3.1, see (Xilinx Answer 22319).

AR# 30941
Date Created 06/18/2008
Last Updated 12/15/2012
Status Active
Type General Article