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AR# 30944

Spartan-3 A / -3 AN / -3 A DDS - My design fails timing in ISE 10.1 but passed in ISE 9.2 due to IF D_DELAY_VALUE

Description

When moving a design that passed timing in ISE 9.2 to ISE 10.1, you might see different timing numbers as the IF D_DELAY_VALUE has changed.

Solution

When using the programmable input delay in the Spartan-3A / -3AN / -3A DSP, the AUTO setting calculates the most optimal delay to be set for each pin based on characterization data to ensure that a zero hold time is achieved. This also assumes that the DCM is not in use for these inputs as the DCM will automatically de-skew the clock for these pins.

In ISE 9.2, the AUTO incorrectly set the IFD_DELAY_VALUE to a value of '0'. However, in ISE 10.1, this was corrected and the IFD_DELAY_VALUE will not be '0' and should be either '4' or '5', depending on device and location.

When the DCM is used for these pins it might result in timing errors in the ISE 10.1 tools compared to a design analyzed from the ISE 9.2 tools. In most cases, when the DCM is in use, the IFD_DELAY_VALUE should be set to '0' for those pins since the DCM automatically deskews the path.

For more information on the input delay functions in the Spartan-3A family, please see the Spartan-3 Generation FPGA User Guide (UG331):

http://www.xilinx.com/support/documentation/user_guides/ug331.pdf

AR# 30944
Date Created 05/28/2008
Last Updated 12/15/2012
Status Active
Type General Article