In channel-bonded designs, it is important to minimize the total skew between lanes that is seen at the receiver. Since each transmitter in a Virtex-4 RocketIO design uses an independently generated high-speed clock to serialize data, there is potential for the transmitter to introduce up to 40 UI or one internal word's worth of skew. In a non-deterministic phase relationship between TXUSRCLK and the internal PMA TXCLK, the internal buffer may add an additional cycle of latency following a reset. By carefully controlling the phase relationship of these clocks and the timing of TXRESET, this skew can be minimized.
The Virtex-4 RocketIO transmitter has the functionality to align the internal PMA TXCLK to an externally provided, frequency locked clock through use of TXSYNC as discussed on page 213 of the Virtex-4 RocketIO Transceiver user's guide:
The recommended implementation to minimize transmit skew is to phase align to an inverted version of TXUSRCLK and use this same inverted_TXUSRCLK clock to drive TXRESET. The recommended method for generating the inverted TXUSRCLK is via a DCM. By using CLK0 to supply TXUSRCLK and CLK180 to supply inverted_TXUSRCLK and keeping both on global routing, the tools will ensure minimum skew between lanes and will maintain a phase relationship between the two clocks.
This will ensure a known reset sequence is propagated to both the read and write sides of the TX Buffer which then ensures similar latencies across all lanes. In the event that TXUSRCLK and TXUSRCLK2 are different speeds, it may be necessary to cascade DCMs.