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AR# 30953

Virtex-5 GTX RocketIO - DFE clock delay calibration override


The GTX RocketIO Transceiver has the potential to use a Digital Feedback Equalization circuit. This circuit can be left in auto calibration mode though there are a number of user modifiable settings that are outlined in the Virtex-5 FPGA RocketIO GTX Transceiver User Guide:


One of these settings is the DFE clock delay which is controlled by the DFE_CFG attribute and the DFECLKDLYADJ ports; and to correctly switch between auto calibration and manual calibration, you need to observe the following recommendations.


To change between manually setting the DFE clock delay and allowing the calibration circuitry to handle this setting internally, a write to DFE_CFG[8] will need to be followed immediately by a GTX_RESET. More specifically, if a 1 to 0 transition is not seen on GTX_RESET following a write to DFE_CFG[8], then the link might break during the recalibration.

AR# 30953
Date Created 05/27/2008
Last Updated 12/15/2012
Status Active
Type General Article