This Release Notes and Known Issues Answer Record is for the Virtex-5 FPGA GTP RocketIO Wizard v1.9 and contains the following information:
- New Features
- Bug Fixes
- Known Issues
- TX Phase Alignment updates - new radio button "Lane-to-lane deskew" on Wizard, page 4. In "Lane-to-lane deskew" mode, Phase Alignment is performed with TX Buffer enabled and TXRESET is applied after Phase Alignment is done.
NOTE: TX Buffer Bypass is an advanced feature and is not recommended for normal operation.
- New Combo box on Wizard, page 4, to select PPM Offset. Based on the PPM Offset, CDR attribute PMA_RX_CFG is optimized for best performance.
- Support for GTP_DUAL Fast Functional Model.
- Synplify 9.2 Support.
- DRC to check compatibility of GTP0 Protocol file and GTP1 Protocol file based on Oversampling.
- RXLOSSOFSYNC Port description corrected on Wizard, page 6.
- TXRESET and RXRESET ports are not driven correctly in multi-tile scenario.
- Wait counter added for locked signal of pll_adv.
- If you set the comma alignment smaller than the datapath width, incoming data can be aligned to multiple positions. The example design does not account for this, and might indicate errors even though data is being received correctly.
- In the case of Clock correction, the GTP wrapper in the Example design is configured correctly, but the block RAM data does not have embedded Clock-correction characters.
- In ES silicon, the logic added to make TX timing more reliable, timing closure at fabric rates of 312.5 MHz and higher might require significant effort. For best results, use a 16- or 20-bit interface for line rates higher than 1.25 Gb/s.
- When migrating designs from version 1.9 of the Wizard from 10.1 to 11.x, the newest Wizard should be used. Re-running v1.9 in the 11.1 design tools is not supported.
- RX buffer bypass in Oversampling mode is not supported.