AR #30957 - 10.1 EDK - "ERROR:MDT - issued from TCL procedure "check_clock_connectivity" line xxx"

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10.1 EDK - "ERROR:MDT - issued from TCL procedure "check_clock_connectivity" line xxx"

AR#	30957
Part	EDK-BSB
Last Modified	2008-05-20 00:00:00.0
Status	Active
Keywords	MPMC, multi, port, memory, control, clock, DRC, Power, PC, 440, Virtex, 5, FXT

Description

Keywords: MPMC, multi, port, memory, control, clock, DRC, Power, PC, 440, Virtex, 5, FXT

When I select the MPMC as my memory controller, I get the following error during platgen:

"ERROR:MDT - issued from TCL procedure "check_clock_connectivity" line 54
ppc440_0 (ppc440_virtex5) -
The MC clock input (CPMMCCLK) must be connected whenever the PPC440MC bus
interface is connected.

ERROR:MDT - platgen failed with errors!
make: *** [implementation/ppc440_0_wrapper.ngc] Error 2
Done!"

Solution

MPMC is not a supported Power PC 440 memory controller in 10.1 or 10.1 Service Pack 1. Full support for Virtex-5 FXT cores including the MPMC will be added in 10.1 Service Pack 2.