| AR# | 30960 |
| Part | EDK-XPS |
| Last Modified | 2008-06-17 00:00:00.0 |
| Status | Active |
| Keywords | clock, DRC, generate |
Keywords: clock, DRC, generate
The following warning occurs after I create a Base System Builder Design:
"WARNING:MDT - The value for the parameter clock_generator_0:C_DCM0_CLKIN_PERIOD
-
C:\Xilinx\10.1\EDK\hw\XilinxProcessorIPLib\pcores\clock_generator_v2_01_a\dat
a\clock_generator_v2_1_0.mpd line 181 is not specified in the MHS. As a
result, the default value (8.000) is used from the MPD. However, the value
should be 10.000000. Please add this parameter in the MHS and set it's value
to : 10.000000 . Please note that this warning will be converted to an ERROR
in EDK 11.1"