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AR# 30971

10.1 Timing Analyzer - Why is the IDELAY TAP delay for Virtex-5 devices reported as 88ps?

Description

Why is the IDELAY TAP delay for Virtex-5 devices reported as 88ps?

Solution

The data sheet has a tap delay of 78 ps per tap, but this is not reflected in Timing Analyzer. The reason is that Timing Analyzer uses worst case values.

Timing Analyzer uses the 78 ps described in the data sheet and then adds IDELAY jitter and IDELAY uncertainty of ~10ps. This 10 ps is the result of characterization tests in the IDELAY.

Timing Analyzer adds the IDELAY base number of 78 ps plus the IDELAY Jitter and IDELAY uncertainty to equal the ~88 ps per tap which is reported in the timing report.

AR# 30971
Date Created 06/12/2008
Last Updated 12/15/2012
Status Active
Type General Article
Tools
  • ISE - 10.1
  • ISE Design Suite - 11.1
  • ISE Design Suite - 11.2
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  • ISE Design Suite - 11.3
  • ISE Design Suite - 11.4
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