^

AR# 31059 12.1 EDK - How can I interface EDK block RAM with the FPGA fabric?

How do I create a block RAM block in EDK that connects one port to the processor bus and the other port to the FPGA fabric?

You can instantiate your block RAM as follows:

# Sub Components
# ###############################################################################
# PortB connected to microblaze and PortA connected to user externals
# PORTB is auto-calculated due to bus_interface connection to the bram_cntlr

BEGIN bram_block
PARAMETER INSTANCE = opb_bram1
PARAMETER HW_VER = 1.00.a
BUS_INTERFACE PORTB = bram_portb
PORT BRAM_Clk_A = sys_clk
PORT BRAM_EN_A = my_bram_en_a
PORT BRAM_WEN_A = my_bram_wen_a
PORT BRAM_Addr_A = my_bram_addr_a
PORT BRAM_Din_A = my_bram_din_a
PORT BRAM_Dout_A = my_bram_dout_a
END



And, define your global ports as follows:

PORT BRAM_Rst_A = BRAM_Rst, DIR = I
PORT BRAM_Clk_A = BRAM_Clk, DIR = I
PORT BRAM_EN_A = my_bram_en_a, DIR = I
PORT BRAM_WEN_A = my_bram_wen_a, DIR = I, VEC = [0:3]
PORT BRAM_Addr_A = my_bram_addr_a, DIR = I, VEC = [0:31]
PORT BRAM_Din_A = my_bram_din_a, DIR = O, VEC = [0:31]
PORT BRAM_Dout_A = my_bram_dout_a, DIR = I, VEC = [0:31]
AR# 31059
Date Created 05/27/2008
Last Updated 11/10/2010
Status Active
Type
Tools
  • EDK - 11.1
  • EDK - 11.2
  • EDK - 11.3
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  • EDK - 11.4
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