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AR# 31060

NCSim - How do I simulate SecureIP with NCSim?

Description

How do I simulate SecureIP with NCSim?

Solution

Xilinx leverages the latest encryption methodology as specified in Verilog LRM - IEEE Std 1364-2005. Simulation models for the Hard-IP such as the PowerPC processor, MGT, and PCIe leverage this technology.

For more information, please refer to the following:

- Synthesis and Simulation Guide at:

http://www.xilinx.com/support/documentation/dt_ise.htm

- SecureIP Master Solution Record (Xilinx Answer 33275)

Starting with 11.1, all hardIP blocks are encrypted using SecureIP. For supported version of NCSim, please refer to the Synthesis and Simulation Guide.

Multi-Step Process with precompiled libraries:

1. Run the CompXLib utility to compile Xilinx libraries. For usage information of this tool, please refer to Command Line Tools User Guide at:

http://www.xilinx.com/support/documentation/dt_ise.htm

- CompXLib compiles all the libraries and updates CDS.lib and HDL.var files with the library mappings.

- The library mappings include Xilinx SecureIP libraries.

2. Run ncvlog, ncelab and NCSim. The simulator will automatically pick up the SecureIp libraries based on the mapping in CDS.lib and HDL.var files. Unlike SmartModels, no extra switches or special ENV settings are needed.

Single Step Process

Since users do not use CompXLib to compile Xilinx libraries in a single-step process, CompXLib does not have to be run.

In order to run SecureIP simulation in this process, only one additional switch needs to be added.

-f $XILINX/secureip/ncsim/ncsim_secureip_cell.list.f

For Example:

ncverilog \

<design>.v <testbench>.v \

${Xilinx}/verilog/src/glbl.v \

-f $XILINX/secureip/ncsim/ncsim_secureip_cell.list.f \

-y ${Xilinx}/verilog/src/unisims +libext+.v \

-y ${Xilinx}/verilog/src/simprims +libext+.v \

+access+r+w

AR# 31060
Date Created 08/24/2009
Last Updated 01/30/2013
Status Active
Type General Article