My design is using the FIR Compiler v3.2 with reloadable coefficients. I specify my coefficients to be asymmetrical. However, when I use the reload port to load a new set of coefficients, the FIR Compiler appears to treat my coefficients as symmetrical and only uses the first half of the coefficients that I have loaded.
This is due to a known issue in System Generator for DSP 10.1.01. This version of the tool does not properly simulate asymmetrical coefficients for the reload feature. This issue does not affect hardware or HDL simulation, only the simulation behavior in System Generator.
This issue is resolved in System Generator for DSP 10.1 Service Pack 2.