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AR# 31072

LogiCORE SPI-4.2 (POS PHY LEVEL 4) - Unused IDELAYCTRL fails to assert RDY and causes design to fail


Virtex-5 designs with the SPI-4.2 module might fail to operate in the hardware. Specifically, the SPI-4.2 Sink Core might not lock and the core might not go in frame. The design might function in one set of silicon, but might fail in a newer set of silicon.

This can be due to IDELAYCTRL embedded in the SPI-4.2 module. If the IDELAYCTRL should be placed in a region where it is not needed, the unused IDELAYCTRL might fail to assert RDY, preventing the entire design from operating. Placing IDELAYCTRL in a region where it is not needed is unlikely to happen, but it is possible even for designs without SPI-4.2 core.



Check your design for unused IDELAYCTRL as follows:

Check your existing MAP report file for the following warnings:

"WARNING:Place:851 - The delay controller "pl4_v8_5_pl4_snk_top0/U0/io0/sict1" has been locked with the following location constraint: COMP "pl4_v8_5_pl4_snk_top0/U0/io0/sict1" LOCATE = SITE "IDELAYCTRL_X0Y2" LEVEL 1. However, none of the delay elements calibrated by this controller are being used. The controller will still use up a global clock source from the clock region and consume power. Please refer to the usage document to use the controller efficiently. "

If you do not have this warning message in your MAP report, your design is not subject to this issue.

Starting with ISE 10.1.2 (Service Pack 2), the above WARNING message will change to an ERROR message. At this point, the unnecessary IDELAYCTRL must be removed. SPI-4.2 core may contain IDELAYCTRL embedded in the core netlist. In this case, you will need to re-generate the SPI-4.2 core without the embedded IDELAYCTRL. On page 3 of the SPI-4.2 customization GUI, deselect the option to "Include IDELAYCTRL modules". By default this option is selected, so you must manually deselect this option. (In the XCO file be sure to have: CSET sink_include_idelayctrl=false).

If you suspect that your design contains unused IDELAYCTRL, refer to (Xilinx Answer 30966) for detailed information and a way to work around this issue.

This issue applies to all Virtex-5 devices implemented with SPI-4.2 IP Core v8.5 or earlier, as listed below:

SPI-4.2 v 8.1 released with ISE 8.2i IP Update 1 in July 2006.

SPI-4.2 v 8.2 released with ISE 8.2i IP Update 2 in October 2006.

SPI-4.2 v 8.3 released with ISE 9.1i IP Update 1 in March 2007.

SPI-4.2 v 8.4 released with ISE 9.2i IP Update1 in August 2007.

SPI-4.2 v 8.5 released with ISE Design Suite 10.1 in March 2008.

Starting with SPI-4.2 v8.6, scheduled for release in ISE 10.1 IP Update 3 (September 2008), the option to include IDELAYCTRL in the SPI-4.2 netlist will be removed. Consequently, you must manually place the IDELAYCTRL in selected I/O banks.

For further questions, contact Xilinx Technical Support by opening a WebCase at:


AR# 31072
Date Created 05/29/2008
Last Updated 12/15/2012
Status Active
Type General Article