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AR# 31081

MIG v2.2 - Patch update for MIG v2.2 to address issues with the "Update Design" feature

Description

Problems have been found with the MIG 2.2 Update Design feature, and a patch is required to work around these issues. The issues are detailed below. 

 

This patch is included in the MIG 2.3 release. 

This patch should only be installed when using MIG 2.2.

Solution

The patch can be downloaded from either of the following locations: 

http://www.xilinx.com/txpatches/pub/applications/misc/mig_v2_2_rev1.zip
http://www.xilinx.com/txpatches/pub/applications/misc/mig_v2_2_rev1.tar.gz

The known issues with Update Design addressed in the tactical patch are as follows: 

 

1. Bit notation in output RLOC_ORIGIN constraints might be incorrect. Lower bits will have the correct notation as shown in bit 23 below while the upper bits are incorrect, as follows: 

INST "*/gen_dq[23].u_iob_dq/gen_stg2_*.u_ff_stg2a_rise" RLOC_ORIGIN = X0Y1; 

INST " */gen_dq[%2].u_iob_dq/gen_stg2_*.u_ff_stg2a_rise" RLOC_ORIGIN = X44Y19; 

INST " */gen_dq[%2].u_iob_dq/gen_stg2_*.u_ff_stg2a_rise" RLOC_ORIGIN = X44Y19; 

INST " */gen_dq[%2].u_iob_dq/gen_stg2_*.u_ff_stg2a_rise" RLOC_ORIGIN = X44Y18; 

INST " */gen_dq[%2].u_iob_dq/gen_stg2_*.u_ff_stg2a_rise" RLOC_ORIGIN = X44Y18; 

 

These incorrect constraints will cause errors during NGDBuild similar to: 

 

ERROR:ConstraintSystem:58 - Constraint <INST "  

*/gen_dq[%2].u_iob_dq/gen_stg2_*....> [mig_update.ucf(291)]: INST "  

*/gen_dq[%2].u_iob_dq/gen_stg2_*.u_ff_stg2a_rise" does not match 

any design objects. 

 

 

2. The DQ_IO_MS and DQS_IO_COL parameters in the top-level rtl ddr2_sdram.v/.vhd file of the updated design are specific to the original UCF and not the UCF uploaded to update. 

If the pin-out is modified (a UCF is uploaded to update), these parameters must be updated. Two errors might be seen in the tools, one during MAP and one during PAR.  

 

The following error might occur during MAP if the parameter settings are incorrect: 

 

ERROR:Place:292 - The components 

u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_io/gen_dq[1].u_iob_dq/stg3b_out_fall 

and 

u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_io/gen_dq[2].u_iob_dq/stg3b_out_fall 

seem to be placed / locked to the same site SLICE_X0Y57 

 

 

The following errors will be seen during PAR if the parameter settings are incorrect: 

 

INFO:ParHelpers:197 - Number of "Exact" mode Directed Routing Constraints: 64 

WARNING:ParHelpers:198 - One or more "EXACT" mode Directed Routing constrained net(s) were not successfully routed 

according to the constraint(s). The router attempted to route the net(s) without regard to the constraint. The number 

of nets found with Directed Routing Constraints: 64, number successfully routed using the constraints: 32, number 

failed: 32. The failed nets are listed below. Please use FPGA Editor to determine the cause of the failure. 

Net u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_io/gen_dq[28].u_iob_dq/stg1_out_rise_1s 

Net u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_io/gen_dq[28].u_iob_dq/stg1_out_fall_1s 

Net u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_io/gen_dq[6].u_iob_dq/stg1_out_fall_0s 

Net u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_io/gen_dq[6].u_iob_dq/stg1_out_rise_0s 

 

 

3. In some cases, the RLOC_ORIGIN constraints are incorrect. This will cause one of the two errors in MAP and PAR as mentioned in #2 above. 

 

 

4. In some cases, the resource LOC constraints for the DQS Gate circuit are swapped between different DQS groups. 


There are a total of 3 LOC constraints for each DQS group. 


Below is an example where the DQS Gate constraints are swapped between bytes [2] and [3]: 

 

INST "*/gen_dqs[2].u_iob_dqs/u_iddr_dq_ce" LOC = "ILOGIC_X0Y18"; # Should be ILOGIC_X0Y16 

INST "*/gen_dqs[2].u_iob_dqs/u_iodelay_dq_ce" LOC = "IODELAY_X0Y18"; # Should be IODELAY_X0Y16 

INST "*/gen_dqs[3].u_iob_dqs/u_iddr_dq_ce" LOC = "ILOGIC_X0Y16"; # Should be ILOGIC_X0Y18 

 

 

5. The IDELAYCTRL LOC constraint in the output UCF is specific to the original UCF and not the UCF uploaded to update. If the pin-out is modified (a UCF is uploaded to update), this value must be updated. 

 

 

6. When non-DCI banks are selected for DQ/DQS in Virtex-5 DDR/DDR2 designs, one DM bit allocation was missing in the UCF file. This allocation is correct with the patch. 

 

 

7. When non-DCI banks are selected for DQ, the RLOC constraints on the slave pins are not correct for the ddr2_v5 design. This allocation is correct with the patch. 

 

 

8. For x4 memory parts, MIG 1.73 generates only one data mask per byte and MIG 2.2 generates two data masks per bytes. When a MIG 1.73 UCF is updated, the updated UCF and the RTL generated from 2.2 will not match.

AR# 31081
Date Created 06/02/2008
Last Updated 10/22/2014
Status Active
Type General Article
IP
  • MIG