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AR# 31087

12.1 Timing Analyzer - Why does Timing Analyzer show that I have no clock uncertainty?


When I run Timing Analysis on my design, I notice that none of my paths have clock uncertainty. Should there be no uncertainty over jitter within the components of the FPGA?


For all devices older than Virtex-4 and Virtex-5 devices, Timing Analyzer does not have any information about individual component jitter within the device. This is because only Virtex-4 and Virtex-5 and newer Speed Files store jitter information on the components.

The component jitter for all other devices can be found in their respective User Guides. To obtain the tools to consider jitter for clock uncertainty, you must tell Timing Analyzer what the total jitter is. This can be done within the period constraint. Use the INPUT_JITTER keyword to specify jitter within the PERIOD Constraint:

TIMESPEC "TSidentifier"=PERIOD 'TNM_reference" period {HIGH | LOW} [high_or_low_time] INPUT_JITTER value;

All random jitter values for a particular path should be added quadratically. For example, if the period constraint covers a DCM, BUFG, and a Flip-Flop, you should add up jitter for all three components and input it as the INPUT_JITTER value.

See (Xilinx Answer 23710), (Xilinx Answer 20828), and (Xilinx Answer 10167) for more information on DCM/PLL output jitter.

For more information on PERIOD, see Xilinx White Paper, "What are PERIOD Constraints" (WP257) at:

AR# 31087
Date 12/15/2012
Status Active
Type General Article
  • ISE - 10.1
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