The E-ERR-0009 error message is equivalent to an internal or fatal error. One common cause for this type of message is that the tool has run out of memory during RTL generation.

To work around this issue, you will need to modify your design and possibly the design approach, emphasizing a reduction in memory consumption during Generate -rtl. In some cases dividing the design up into multiple smaller files will allow AccelDSP to pass the Generate -rtl phase.

The AccelDSP User Guide contains good coding style guidelines for targeting m-code to hardware. There are also some free online training videos available which give a good overview of how to target m-code at FPGAs:

http://www.xilinx.com/ise/dsp_design_prod/acceldsp/index.htm

Typically, there is a strong correlation between memory consumption and array size, the number of functions that are called, unrolling FOR loops, and the bit-width for representing the MATLAB variables in the Fixed Point Representation. Each of these topics have its own approach for reducing memory consumption.

Browsing through the Fixed Point report is a good starting point to observe the type of hierarchy, in terms of function calls (which translate to hardware) your design has generated, as well as the size and quantity of variables which will need to be stored.

Multiple function calls

Since each call to a function call is expanded "in-line", the contents of that function are duplicated when it is called multiple times. (You only have to worry about functions that are called from within the Design Function on down in the calling hierarchy; what is referred to as a "sub-function".) If a function contains a lot of behavior, then for every call to this design function you will expand the memory (and hardware) consumption.

To reduce this consumption due to multiple calls to a function, it is recommended that you keep the number of calls to a sub-function minimum. For example, rather than putting a call to the same function in the THEN and ELSE clause of an IF Statement with only changes in the input arguments, use the IF Statement to set input arguments, and then, after the IF Statement call the design function (this way, you have only one instance of the call). In some cases, this is not desired and it might be required that a function be called explicitly multiple times in order to achieve the desired system performance. However, if latency is not an issue, you will save resources by sharing the function in this way.

Loops

FOR loops that are unrolled usually increase the sampling rate, but the body of the FOR loop is duplicated to achieve this. Therefore, keep large FOR loops fully rolled to reduce memory consumption.

Variable shape

To reduce memory consumption due to the size of an array, be it Vector or Matrix, you can map the array to a memory element via the 'MemMap" Directive. To achieve a higher sampling rate, AccelDSP will attempt to 'scalarize" the arrays. Therefore, if your array was a NxM Matrix, AccelDSP would create N*M different scalar values to represent that array. Each of the individual scalars is then maintained and scheduled. If you map the array to a memory element, then you do not have the explosion of scalars.

Variable Quantization

The bit-width is closely related to the Quantization value. AccelDSP during Generate Fixed Point attempts to keep errors due to fidelity to a minimum. Therefore, after most arithmetic operations, the number of bits used to represent the result grows. If left unchecked, the resulting Fixed Point Representation will have a large number of bits to represent most MATLAB Variables. This results in requiring more interconnect (wires) and storage elements (Flip-Flops) in the resulting circuit. While this does not affect memory consumption during Generate RTL as the other topics mentioned, it has a strong affect on the size of the circuit, and the ability of PAR to route the circuit during the later stages. It is always best to review the Fixed Point Report and determine what variables can be reduced in bit-width with little affect on the fidelity of the design. It is recommended to use 'accel_probe" to help identify fidelity issues.