When I instantiate a VIO/ILA/ATC2 ChipScope core in my design and implement, an error occurs similar to the following at the NGDBuild stage:
"ERROR:NgdBuild:76 - File "<file_path>/vio.ngc" cannot be merged into block "vio" (TYPE="vio") because one or morepins on the block, including pin "sync_out", were not found in the file."
How can I work around this error?
Signal bit-widths for ChipScope cores must be declared as vectors. For example, the signal "sync_out" should be declared as "wire [0:0] sync_out". Also, in the instantiation template for the VIO core, this convention must be used. The "vio.v" file generated from CORE Generator shows this in the module declaration, following this format should work around this error. If they are declared as just a std_logic or wire, "ERROR:NgdBuild:76" will occur at the Translate stage of implementation. This is because the core instantiation will not match up with the netlist.
For example, a one bit port "sync_out" would be declared as follows:
input [0:0] sync_out
sync_out : in std_logic_vector(0 downto 0);