UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 31116

LogiCORE CTC Decoder v3.0:- Why, if 8 bit is selected for soft input/extrinsic data width, does the core's performance reduce?

Description

Why, when 8 bits is selected for the soft input data width and the extrinsic data, does the core use three BUFGs and thus reduces the performance of the core?

Solution

If the core selects 6 bits for the soft input/extrinsic data width a performance of ~205 MHz in a Virtex-5 xc5vlx110-ff676-1 can be expected.

However, if 8 bits is selected, the performance drops off to ~164 MHz. This results from the fact that when the netlist is generated, three BUFGs are used to reduce the fan out, which affects the performance.

If you have a requirement for a higher performance than 164 MHz, please open a webcase. Include the following:

XCO file

Device

Speedgrade

Please see (Xilinx Answer 29447) for a detailed list of LogiCORE 802.16E Convolutional Turbo Code (CTC) Decoder Release Notes and Known Issues.

AR# 31116
Date Created 06/17/2008
Last Updated 12/15/2012
Status Active
Type General Article