We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 31122

10.1 PAR - Passing SPI-4.2 designs fail in Service Pack 1


Formerly passing designs in ISE 10.1 now fail with ISE 10.1 Service Pack 1 with the following error:

ERROR:Place:850 - Delay element

"core_pl4_snk_top0/U0/io0/dpa2/dpa_top0/DATAPAIR0/SLAVE_DELAY" has been

placed at IODELAY_X0Y2, however, the delay controller that calibrates this

element has not been used. If a delay controller has been instantiated and a

location constraint has been applied to it, please constraint this delay

element to the same region. If a delay controller has not been instantiated

please instantiate one. Please refer to the usage document to use the delay

controller efficiently.


This problem has been fixed in the latest 10.1 Service Pack available at:


The first service pack containing the fix is 10.1 Service Pack 2 .

AR# 31122
Date 12/15/2012
Status Active
Type General Article
Page Bookmarked