I made a change to a timing constraint in my design, and now MAP is no longer able to fit the design. The following errors are printed:
Running delay-based LUT packing...
ERROR:Pack:1653 - At least one timing constraint is impossible to meet because
component delays alone exceed the constraint. A timing constraint summary
below shows the failing constraints (preceded with an Asterisk (*)). Please
use the Timing Analyzer (GUI) or TRCE (command line) with the Mapped NCD and
PCF files to identify which constraints and paths are failing because of the
component delays alone. If the failing path(s) is mapped to Xilinx components
as expected, consider relaxing the constraint. If it is not mapped to
components as expected, re-evaluate your HDL and how synthesis is optimizing
the path. To allow the tools to bypass this error, set the environment
variable XIL_TIMING_ALLOW_IMPOSSIBLE to 1.
For more information about the Timing Analyzer, consult the Xilinx Timing
Analyzer Reference manual; for more information on TRCE, consult the Xilinx
Development System Reference Guide "TRACE" chapter.
ERROR:Pack:2310 - Too many comps of type "SLICEL" found to fit this device.
The PACK:2310 error is misleading. MAP stopped processing the design due to an impossible timing constraint where component delays and best case timing delays violate a constraint. MAP then incorrectly used the incompletely packed design to print a design summary which indicates that SLICEL components are over utilized. This is misleading because the timing failure is the actual root cause of this failure. This messaging issue will be corrected in ISE version 11.1.
See (Xilinx Answer 23165) for more information about debugging impossible timing errors.