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# AR# 31151

## Description

The following error occurs in XST after Advanced HDL synthesis.

"INTERNAL_ERROR:Xst:cmain.c:3378:1.25.10.1 - To resolve this error, please consult the Answers Database and other online resources at http://support.xilinx.com"

Why does this error occur?

## Solution

One possible cause for this Internal error is the following construct:

reg [4:0] test;

always @(posedge clk or posedge rst) begin

if (rst) begin

test <= TCQ 'b0;

end else begin

test <= a1 + a2 + a3 + a4 + a5 +a6 + a7 + a8+ a9 + a10 + a11 + a12 + a13 + a14 + a15 + a16 + a17 + a18;

The destination is a 5-bit signal. The expression assigned when the reset is inactive is a sum of 18 1-bit operands. Logically, the result values are between 0 and 18 and this is perfectly covered with 5-bit. However, due to some optimizations, 3 of the 18 operands are simplified to zero. As a consequence, XST figures out that the result now only needs 4-bit, therefore, creating a data representation for this sum that is not aligned with the destination. This badly aligned arithmetic construct eventually causes XST to exit with an internal error.

To work around this issue, force the extension of all the operands to 5-bit.

Example :

wire [4:0] wa_a1;

assign wa_a1= {4'b0, a1};

wire [4:0] wa_a2;

assign wa_a2= {4'b0, a2};

.

.

.

wire [4:0] wa_a18;

assign wa_a18= {4'b0, a18};

test <= wa_a1+wa_a2+..... . ........+wa_a18;

This is a problem in XST that will be fixed in a future release of the software.

AR# 31151
Date 12/15/2012
Status Active
Type General Article
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