When a processor accesses peripherals with high frequencies connected to the XPS_EPC, interface (i.e. PRH_* interface), the core will assert PRH_Rdy signal almost immediately after PRH_CS_n is triggered, which is expected.
However, when the C_PRHx_RDY_WIDTH parameter is set to 2 microseconds or greater, the XPS_EPC core will wait for PRH_Rdy signal for approximately 1.27 microseconds. Why does this occur?
The EPC core's intended design targets are peripherals, such as USB, SMSC LAN, etc. These devices operate at higher frequencies, and peripherals that operate at lower frequency ranges are not recommended for use with the XPS_EPC core.
However, if lower frequencies are necessary for your specific design, you can add two generic parameters to the code that can be used to work with lower frequencies. If the parameters are not declared in the instantiation of plb_v46_slave_single, then the default value of 1 will be used. The two parameters are described below:
C_BUS2CORE_CLK_RATIO (default = 1) - Specifies the clock ratio from BUS to Core allowing the core to operate at a slower than the bus clock rate. A value of 1 represents 1:1 and a value of 2 represents 2:1 where the bus clock is twice as fast as the core clock.
C_INCLUDE_DPHASE_TIMER (default = 1) - Include or exclude the data phase timeout timer.
0 = exclude data phase timeout timer
1 = include data phase timeout timer
These generic parameters should be added only when interfacing to peripherals that operate at a slower clock frequency than the processor and cases where slave timeout is not an issue, since changing C_INCLUDE_DPHASE_TIMER to a "0" removes the timeout functionality.
To edit the core, navigate to the %Xilinx_EDK/hw/XilinxProcessorIPLib/pcores/xps_epc_v1_00_a/hdl/vhdl directory and open the "xps_epc.vhd" file. Add the following parameters on line 765, as shown below:
C_SPLB_P2P => C_SPLB_P2P,
C_BUS2CORE_CLK_RATIO => 1, -- Add this line
C_INCLUDE_DPHASE_TIMER => 0, -- Add this line
C_SPLB_MID_WIDTH => C_SPLB_MID_WIDTH