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AR# 31161

Endpoint Block Plus Wrapper v1.8 for PCI Express - TRN_TSRC_RDY_N deassertion causes continuous TRN_TDST_RDY_N deassertions

Description

v1.8, v1.6.1, v1.7.1 Known Issue

When a memory write is transmitted following a completion, the core deasserts TRN_TDST_RDY_N for two clock cycles while it changes transmit FIFO channels on the Integrated Block. If I simultaneously deassert TRN_TSRC_RDY_N, it causes the wrapper to get caught in a loop of continually asserting and deasserting TRN_TDST_RDY_N.

Solution

The problem is illustrated in the following figure. This problem only occurs on a TLP following a completion TLP that is not also a Completion TLP (for example, a Memory Write TLP following a Completion TLP).

To work around this problem, do not deassert TRN_TSRC_RDY_N in response to the first deassertion of TRN_TDST_RDY_N. It is acceptable to deassert TRN_TSRC_RDY_N any time after this first deassertion of TRN_TDST_RDY_N.

This issue is fixed in v1.9, which will be available in 10.1sp3 IP Update 3.

Revision History

09/10/2008 - Updated with fix information.

06/18/2008 - Updated for v1.8 core.

06/12/2008 - Initial Release.

AR# 31161
Date Created 06/12/2008
Last Updated 12/15/2012
Status Active
Type General Article