We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 31165

Endpoint Block Plus Wrapper v1.8, Endpoint PIPE v1.7, and Endpoint Soft-IP v3.6 for PCI Express - Downstream Port Model Testbench uses the word "type" causing problems with System Verilog


The word "type" is used in the downstream port testbench file pci_exp_userap_com.v. This is a keyword in System Verilog and causes problems during compilation.


To work around this issue, perform a search and replace on "type", renaming it something else (for example, "frame_type").

This problem will be corrected in a future release.

Revision History

06/18/2008 - Added BP v1.8

06/12/2008 - Initial Release

AR# 31165
Date Created 06/12/2008
Last Updated 03/01/2013
Status Active
Type General Article