AR #31179 - 10.1EDK SP2, apu_fpu_virtex5_v1_00_a - Enabling FPU Exceptions could cause Data Corruption.

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10.1EDK SP2, apu_fpu_virtex5_v1_00_a - Enabling FPU Exceptions could cause Data Corruption.

AR#	31179
Part	IP-Processor
Last Modified	2008-06-26 00:00:00.0
Status	Active
Keywords	FPU, Virtex 5FXT

Description

Keywords: FPU, Virtex 5FXT

This issue relates to a very unlikely scenario in which data corruption or processor hangs can occur if the FPU is used with floating point exceptions enabled by setting one or both of the FE[0,1] bits in the MSR.

FPU exceptions are disabled in the default mode. The Xilinx GNU compiler (standalone EABI) and the Board-Support Package code do not contain instructions that enable the FPU exceptions. Thus, this issue will not occur when using the Xilinx GNU compiler and/or Board-Support Package.

Solution

To work around this, disable the FPU exceptions and, if using a third-party compiler or OS, assure that floating point exceptions are not enabled (i.e. bits FE0 and FE1 in the machine state register (MSR) are always set to zero).

The issue will be fixed in the EDK 10.1 Service Pack 3. It will be available at:
http://www.xilinx.com/xlnx/xil_sw_updates_home.jsp