AR #31181 - 10.1 EDK SP2, apu_fpu_virtex5_v1_00_a - XST synthesis errors out when C_USE_RLOCS=1

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10.1 EDK SP2, apu_fpu_virtex5_v1_00_a - XST synthesis errors out when C_USE_RLOCS=1

AR#	31181
Part	IP-Processor
Last Modified	2008-06-19 00:00:00.0
Status	Active
Keywords	FPU, Virtex-5 FXT

Description

Keywords: FPU, Virtex-5 FXT

The default FPU configuration, both when creating a project using Base System Builder and when adding the FPU to a system manually, has the parameters C_LATENCY_CONF=1 and C_USE_RLOCS=0. Any system using these default parameters will build successfully. The problem only arises if the user wants to modify this configuration to set C_USE_RLOCS=1 to achieve higher performance. In this scenario, Platgen will attempt to include a non-existent netlist file in the design, and XST will error out during the final phase of netlist generation with the following:

" Running XST synthesis ...
ERROR:Xst:1673 - Processing TIMESPEC TS_AREA_DEF: Unrecognized type.
ERROR:Xst:1489 - Constraint annotation failed.
make: *** [implementation/system.ngc] Error 1 "

Solution

To fix this issue, replace the FPU's erroneous VHDL wrapper file from your EDK repository. The corrected "apu_fpu_virtex5.vhd" wrapper file is available at:
ftp://ftp.xilinx.com/pub/applications/misc/apu_fpu_virtex5.zip

1. Unzip and replace the existing "apu_fpu_virtex5.vhd" from the synhdl/vhdl directory of EDK build
(i.e., %Xilinx/EDK/hw/XilinxProcessorIPLib/pcores/apu_fpu_virtex5_v1_00_a/synhdl/vhdl ) with the new file.
2. Run '"Clean Hardware" from the Hardware menu and rebuild your EDK project.

This issue will be fixed in EDK 10.1 Service Pack 3. It will be available at:
http://www.xilinx.com/xlnx/xil_sw_updates_home.jsp